diff options
21 files changed, 3664 insertions, 2 deletions
diff --git a/internal/rosa/package/spirv/0001-grammar-and-header-changes-for-SPV_INTEL_predicated_.patch b/internal/rosa/package/spirv/0001-grammar-and-header-changes-for-SPV_INTEL_predicated_.patch new file mode 100644 index 00000000..fd08ff5e --- /dev/null +++ b/internal/rosa/package/spirv/0001-grammar-and-header-changes-for-SPV_INTEL_predicated_.patch @@ -0,0 +1,341 @@ +From b8a32968473ce852a809b9de5f04f02a5a9dfa78 Mon Sep 17 00:00:00 2001 +From: Yury Plyakhin <yury.plyakhin@intel.com> +Date: Wed, 29 Apr 2026 07:52:53 -0700 +Subject: [PATCH 01/26] grammar and header changes for SPV_INTEL_predicated_io + (#585) + +--- + include/spirv/unified1/spirv.bf | 3 ++ + .../spirv/unified1/spirv.core.grammar.json | 34 +++++++++++++++++++ + include/spirv/unified1/spirv.cs | 3 ++ + include/spirv/unified1/spirv.h | 8 +++++ + include/spirv/unified1/spirv.hpp | 8 +++++ + include/spirv/unified1/spirv.hpp11 | 8 +++++ + include/spirv/unified1/spirv.json | 3 ++ + include/spirv/unified1/spirv.lua | 3 ++ + include/spirv/unified1/spirv.py | 3 ++ + include/spirv/unified1/spv.d | 3 ++ + 10 files changed, 76 insertions(+) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index b705259..0fd8703 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -1426,6 +1426,7 @@ namespace Spv + UntypedVariableLengthArrayINTEL = 6243, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, ++ PredicatedIOINTEL = 6257, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2694,6 +2695,8 @@ namespace Spv + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, ++ OpPredicatedLoadINTEL = 6258, ++ OpPredicatedStoreINTEL = 6259, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 22f5fe9..0a282c5 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -11598,6 +11598,34 @@ + "provisional" : true, + "version" : "None" + }, ++ { ++ "opname" : "OpPredicatedLoadINTEL", ++ "class" : "Memory", ++ "opcode" : 6258, ++ "operands" : [ ++ { "kind" : "IdResultType" }, ++ { "kind" : "IdResult" }, ++ { "kind" : "IdRef", "name" : "Pointer" }, ++ { "kind" : "IdRef", "name" : "Predicate" }, ++ { "kind" : "IdRef", "name" : "Default Value" }, ++ { "kind" : "MemoryAccess", "quantifier" : "?" } ++ ], ++ "capabilities" : [ "PredicatedIOINTEL" ], ++ "version" : "None" ++ }, ++ { ++ "opname" : "OpPredicatedStoreINTEL", ++ "class" : "Memory", ++ "opcode" : 6259, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "Pointer" }, ++ { "kind" : "IdRef", "name" : "Object" }, ++ { "kind" : "IdRef", "name" : "Predicate" }, ++ { "kind" : "MemoryAccess", "quantifier" : "?" } ++ ], ++ "capabilities" : [ "PredicatedIOINTEL" ], ++ "version" : "None" ++ }, + { + "opname" : "OpGroupIMulKHR", + "class" : "Group", +@@ -18659,6 +18687,12 @@ + "provisional" : true, + "version": "None" + }, ++ { ++ "enumerant" : "PredicatedIOINTEL", ++ "value" : 6257, ++ "extensions" : [ "SPV_INTEL_predicated_io" ], ++ "version" : "None" ++ }, + { + "enumerant" : "GroupUniformArithmeticKHR", + "value" : 6400, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 2f8c1ff..375dd0b 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -1425,6 +1425,7 @@ namespace Spv + UntypedVariableLengthArrayINTEL = 6243, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, ++ PredicatedIOINTEL = 6257, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2693,6 +2694,8 @@ namespace Spv + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, ++ OpPredicatedLoadINTEL = 6258, ++ OpPredicatedStoreINTEL = 6259, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index d00cf0f..9233ff0 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -1396,6 +1396,7 @@ typedef enum SpvCapability_ { + SpvCapabilityUntypedVariableLengthArrayINTEL = 6243, + SpvCapabilitySpecConditionalINTEL = 6245, + SpvCapabilityFunctionVariantsINTEL = 6246, ++ SpvCapabilityPredicatedIOINTEL = 6257, + SpvCapabilityGroupUniformArithmeticKHR = 6400, + SpvCapabilityTensorFloat32RoundingINTEL = 6425, + SpvCapabilityMaskedGatherScatterINTEL = 6427, +@@ -2628,6 +2629,8 @@ typedef enum SpvOp_ { + SpvOpSpecConstantArchitectureINTEL = 6252, + SpvOpSpecConstantCapabilitiesINTEL = 6253, + SpvOpConditionalCopyObjectINTEL = 6254, ++ SpvOpPredicatedLoadINTEL = 6258, ++ SpvOpPredicatedStoreINTEL = 6259, + SpvOpGroupIMulKHR = 6401, + SpvOpGroupFMulKHR = 6402, + SpvOpGroupBitwiseAndKHR = 6403, +@@ -3510,6 +3513,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy + case SpvOpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpPredicatedLoadINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpPredicatedStoreINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; +@@ -4517,6 +4522,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityUntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL"; + case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; ++ case SpvCapabilityPredicatedIOINTEL: return "PredicatedIOINTEL"; + case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +@@ -5575,6 +5581,8 @@ inline const char* SpvOpToString(SpvOp value) { + case SpvOpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case SpvOpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case SpvOpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; ++ case SpvOpPredicatedLoadINTEL: return "OpPredicatedLoadINTEL"; ++ case SpvOpPredicatedStoreINTEL: return "OpPredicatedStoreINTEL"; + case SpvOpGroupIMulKHR: return "OpGroupIMulKHR"; + case SpvOpGroupFMulKHR: return "OpGroupFMulKHR"; + case SpvOpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 462c3f6..055086c 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -1392,6 +1392,7 @@ enum Capability { + CapabilityUntypedVariableLengthArrayINTEL = 6243, + CapabilitySpecConditionalINTEL = 6245, + CapabilityFunctionVariantsINTEL = 6246, ++ CapabilityPredicatedIOINTEL = 6257, + CapabilityGroupUniformArithmeticKHR = 6400, + CapabilityTensorFloat32RoundingINTEL = 6425, + CapabilityMaskedGatherScatterINTEL = 6427, +@@ -2624,6 +2625,8 @@ enum Op { + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, ++ OpPredicatedLoadINTEL = 6258, ++ OpPredicatedStoreINTEL = 6259, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +@@ -3506,6 +3509,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpPredicatedLoadINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpPredicatedStoreINTEL: *hasResult = false; *hasResultType = false; break; + case OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; + case OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; + case OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; +@@ -4513,6 +4518,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityUntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL"; + case CapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case CapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; ++ case CapabilityPredicatedIOINTEL: return "PredicatedIOINTEL"; + case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case CapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +@@ -5571,6 +5577,8 @@ inline const char* OpToString(Op value) { + case OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; ++ case OpPredicatedLoadINTEL: return "OpPredicatedLoadINTEL"; ++ case OpPredicatedStoreINTEL: return "OpPredicatedStoreINTEL"; + case OpGroupIMulKHR: return "OpGroupIMulKHR"; + case OpGroupFMulKHR: return "OpGroupFMulKHR"; + case OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index 41ebe91..0d85dfe 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -1392,6 +1392,7 @@ enum class Capability : unsigned { + UntypedVariableLengthArrayINTEL = 6243, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, ++ PredicatedIOINTEL = 6257, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2624,6 +2625,8 @@ enum class Op : unsigned { + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, ++ OpPredicatedLoadINTEL = 6258, ++ OpPredicatedStoreINTEL = 6259, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +@@ -3506,6 +3509,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case Op::OpSpecConstantArchitectureINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpSpecConstantCapabilitiesINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConditionalCopyObjectINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpPredicatedLoadINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpPredicatedStoreINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpGroupIMulKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpGroupFMulKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpGroupBitwiseAndKHR: *hasResult = true; *hasResultType = true; break; +@@ -4513,6 +4518,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::UntypedVariableLengthArrayINTEL: return "UntypedVariableLengthArrayINTEL"; + case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL"; + case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL"; ++ case Capability::PredicatedIOINTEL: return "PredicatedIOINTEL"; + case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +@@ -5571,6 +5577,8 @@ inline const char* OpToString(Op value) { + case Op::OpSpecConstantArchitectureINTEL: return "OpSpecConstantArchitectureINTEL"; + case Op::OpSpecConstantCapabilitiesINTEL: return "OpSpecConstantCapabilitiesINTEL"; + case Op::OpConditionalCopyObjectINTEL: return "OpConditionalCopyObjectINTEL"; ++ case Op::OpPredicatedLoadINTEL: return "OpPredicatedLoadINTEL"; ++ case Op::OpPredicatedStoreINTEL: return "OpPredicatedStoreINTEL"; + case Op::OpGroupIMulKHR: return "OpGroupIMulKHR"; + case Op::OpGroupFMulKHR: return "OpGroupFMulKHR"; + case Op::OpGroupBitwiseAndKHR: return "OpGroupBitwiseAndKHR"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 0a200b2..ec778af 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -1358,6 +1358,7 @@ + "UntypedVariableLengthArrayINTEL": 6243, + "SpecConditionalINTEL": 6245, + "FunctionVariantsINTEL": 6246, ++ "PredicatedIOINTEL": 6257, + "GroupUniformArithmeticKHR": 6400, + "TensorFloat32RoundingINTEL": 6425, + "MaskedGatherScatterINTEL": 6427, +@@ -2595,6 +2596,8 @@ + "OpSpecConstantArchitectureINTEL": 6252, + "OpSpecConstantCapabilitiesINTEL": 6253, + "OpConditionalCopyObjectINTEL": 6254, ++ "OpPredicatedLoadINTEL": 6258, ++ "OpPredicatedStoreINTEL": 6259, + "OpGroupIMulKHR": 6401, + "OpGroupFMulKHR": 6402, + "OpGroupBitwiseAndKHR": 6403, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index e612025..b883dd8 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -1383,6 +1383,7 @@ spv = { + UntypedVariableLengthArrayINTEL = 6243, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, ++ PredicatedIOINTEL = 6257, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2615,6 +2616,8 @@ spv = { + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, ++ OpPredicatedLoadINTEL = 6258, ++ OpPredicatedStoreINTEL = 6259, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index 1085498..590ee22 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -1354,6 +1354,7 @@ spv = { + 'UntypedVariableLengthArrayINTEL' : 6243, + 'SpecConditionalINTEL' : 6245, + 'FunctionVariantsINTEL' : 6246, ++ 'PredicatedIOINTEL' : 6257, + 'GroupUniformArithmeticKHR' : 6400, + 'TensorFloat32RoundingINTEL' : 6425, + 'MaskedGatherScatterINTEL' : 6427, +@@ -2558,6 +2559,8 @@ spv = { + 'OpSpecConstantArchitectureINTEL' : 6252, + 'OpSpecConstantCapabilitiesINTEL' : 6253, + 'OpConditionalCopyObjectINTEL' : 6254, ++ 'OpPredicatedLoadINTEL' : 6258, ++ 'OpPredicatedStoreINTEL' : 6259, + 'OpGroupIMulKHR' : 6401, + 'OpGroupFMulKHR' : 6402, + 'OpGroupBitwiseAndKHR' : 6403, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index c9cde5d..0323867 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -1428,6 +1428,7 @@ enum Capability : uint + UntypedVariableLengthArrayINTEL = 6243, + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, ++ PredicatedIOINTEL = 6257, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -2696,6 +2697,8 @@ enum Op : uint + OpSpecConstantArchitectureINTEL = 6252, + OpSpecConstantCapabilitiesINTEL = 6253, + OpConditionalCopyObjectINTEL = 6254, ++ OpPredicatedLoadINTEL = 6258, ++ OpPredicatedStoreINTEL = 6259, + OpGroupIMulKHR = 6401, + OpGroupFMulKHR = 6402, + OpGroupBitwiseAndKHR = 6403, +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0002-header-updates-for-SPV_INTEL_rounded_divide_sqrt-582.patch b/internal/rosa/package/spirv/0002-header-updates-for-SPV_INTEL_rounded_divide_sqrt-582.patch new file mode 100644 index 00000000..7a9ef3a7 --- /dev/null +++ b/internal/rosa/package/spirv/0002-header-updates-for-SPV_INTEL_rounded_divide_sqrt-582.patch @@ -0,0 +1,170 @@ +From 948a3b0997e2dffea5484b3df7bd5590c5b844cc Mon Sep 17 00:00:00 2001 +From: Ben Ashbaugh <ben.ashbaugh@intel.com> +Date: Wed, 29 Apr 2026 08:10:46 -0700 +Subject: [PATCH 02/26] header updates for SPV_INTEL_rounded_divide_sqrt (#582) + +--- + include/spirv/unified1/spirv.bf | 1 + + include/spirv/unified1/spirv.core.grammar.json | 6 ++++++ + include/spirv/unified1/spirv.cs | 1 + + include/spirv/unified1/spirv.h | 2 ++ + include/spirv/unified1/spirv.hpp | 2 ++ + include/spirv/unified1/spirv.hpp11 | 2 ++ + include/spirv/unified1/spirv.json | 1 + + include/spirv/unified1/spirv.lua | 1 + + include/spirv/unified1/spirv.py | 1 + + include/spirv/unified1/spv.d | 1 + + 10 files changed, 18 insertions(+) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 0fd8703..3d24085 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -1427,6 +1427,7 @@ namespace Spv + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, + PredicatedIOINTEL = 6257, ++ RoundedDivideSqrtINTEL = 6265, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 0a282c5..4fc0ec9 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -18693,6 +18693,12 @@ + "extensions" : [ "SPV_INTEL_predicated_io" ], + "version" : "None" + }, ++ { ++ "enumerant" : "RoundedDivideSqrtINTEL", ++ "value" : 6265, ++ "extensions" : [ "SPV_INTEL_rounded_divide_sqrt" ], ++ "version": "None" ++ }, + { + "enumerant" : "GroupUniformArithmeticKHR", + "value" : 6400, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 375dd0b..35b9aff 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -1426,6 +1426,7 @@ namespace Spv + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, + PredicatedIOINTEL = 6257, ++ RoundedDivideSqrtINTEL = 6265, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 9233ff0..a9e4998 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -1397,6 +1397,7 @@ typedef enum SpvCapability_ { + SpvCapabilitySpecConditionalINTEL = 6245, + SpvCapabilityFunctionVariantsINTEL = 6246, + SpvCapabilityPredicatedIOINTEL = 6257, ++ SpvCapabilityRoundedDivideSqrtINTEL = 6265, + SpvCapabilityGroupUniformArithmeticKHR = 6400, + SpvCapabilityTensorFloat32RoundingINTEL = 6425, + SpvCapabilityMaskedGatherScatterINTEL = 6427, +@@ -4523,6 +4524,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case SpvCapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; + case SpvCapabilityPredicatedIOINTEL: return "PredicatedIOINTEL"; ++ case SpvCapabilityRoundedDivideSqrtINTEL: return "RoundedDivideSqrtINTEL"; + case SpvCapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case SpvCapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case SpvCapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 055086c..6676d71 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -1393,6 +1393,7 @@ enum Capability { + CapabilitySpecConditionalINTEL = 6245, + CapabilityFunctionVariantsINTEL = 6246, + CapabilityPredicatedIOINTEL = 6257, ++ CapabilityRoundedDivideSqrtINTEL = 6265, + CapabilityGroupUniformArithmeticKHR = 6400, + CapabilityTensorFloat32RoundingINTEL = 6425, + CapabilityMaskedGatherScatterINTEL = 6427, +@@ -4519,6 +4520,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilitySpecConditionalINTEL: return "SpecConditionalINTEL"; + case CapabilityFunctionVariantsINTEL: return "FunctionVariantsINTEL"; + case CapabilityPredicatedIOINTEL: return "PredicatedIOINTEL"; ++ case CapabilityRoundedDivideSqrtINTEL: return "RoundedDivideSqrtINTEL"; + case CapabilityGroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case CapabilityTensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case CapabilityMaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index 0d85dfe..e08b65b 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -1393,6 +1393,7 @@ enum class Capability : unsigned { + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, + PredicatedIOINTEL = 6257, ++ RoundedDivideSqrtINTEL = 6265, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +@@ -4519,6 +4520,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::SpecConditionalINTEL: return "SpecConditionalINTEL"; + case Capability::FunctionVariantsINTEL: return "FunctionVariantsINTEL"; + case Capability::PredicatedIOINTEL: return "PredicatedIOINTEL"; ++ case Capability::RoundedDivideSqrtINTEL: return "RoundedDivideSqrtINTEL"; + case Capability::GroupUniformArithmeticKHR: return "GroupUniformArithmeticKHR"; + case Capability::TensorFloat32RoundingINTEL: return "TensorFloat32RoundingINTEL"; + case Capability::MaskedGatherScatterINTEL: return "MaskedGatherScatterINTEL"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index ec778af..bd3f41b 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -1359,6 +1359,7 @@ + "SpecConditionalINTEL": 6245, + "FunctionVariantsINTEL": 6246, + "PredicatedIOINTEL": 6257, ++ "RoundedDivideSqrtINTEL": 6265, + "GroupUniformArithmeticKHR": 6400, + "TensorFloat32RoundingINTEL": 6425, + "MaskedGatherScatterINTEL": 6427, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index b883dd8..347e010 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -1384,6 +1384,7 @@ spv = { + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, + PredicatedIOINTEL = 6257, ++ RoundedDivideSqrtINTEL = 6265, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index 590ee22..a5c118d 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -1355,6 +1355,7 @@ spv = { + 'SpecConditionalINTEL' : 6245, + 'FunctionVariantsINTEL' : 6246, + 'PredicatedIOINTEL' : 6257, ++ 'RoundedDivideSqrtINTEL' : 6265, + 'GroupUniformArithmeticKHR' : 6400, + 'TensorFloat32RoundingINTEL' : 6425, + 'MaskedGatherScatterINTEL' : 6427, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 0323867..781154a 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -1429,6 +1429,7 @@ enum Capability : uint + SpecConditionalINTEL = 6245, + FunctionVariantsINTEL = 6246, + PredicatedIOINTEL = 6257, ++ RoundedDivideSqrtINTEL = 6265, + GroupUniformArithmeticKHR = 6400, + TensorFloat32RoundingINTEL = 6425, + MaskedGatherScatterINTEL = 6427, +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0003-Add-SPV_MESA_fragment_coverage_mask-enumerants-580.patch b/internal/rosa/package/spirv/0003-Add-SPV_MESA_fragment_coverage_mask-enumerants-580.patch new file mode 100644 index 00000000..5bb3f9f3 --- /dev/null +++ b/internal/rosa/package/spirv/0003-Add-SPV_MESA_fragment_coverage_mask-enumerants-580.patch @@ -0,0 +1,282 @@ +From 157de8e260e9362225c0ce9a6675d034968abe15 Mon Sep 17 00:00:00 2001 +From: mjkrol <mjkrol@gmail.com> +Date: Wed, 29 Apr 2026 17:42:37 +0200 +Subject: [PATCH 03/26] Add SPV_MESA_fragment_coverage_mask enumerants (#580) + +Reserve BuiltIn FragmentCoverageMaskMESA (4096) and Capability +FragmentCoverageMESA (4097) for SPV_MESA_fragment_coverage_mask. +--- + include/spirv/unified1/spirv.bf | 2 ++ + include/spirv/unified1/spirv.core.grammar.json | 13 +++++++++++++ + include/spirv/unified1/spirv.cs | 2 ++ + include/spirv/unified1/spirv.h | 4 ++++ + include/spirv/unified1/spirv.hpp | 4 ++++ + include/spirv/unified1/spirv.hpp11 | 4 ++++ + include/spirv/unified1/spirv.json | 2 ++ + include/spirv/unified1/spirv.lua | 2 ++ + include/spirv/unified1/spirv.py | 2 ++ + include/spirv/unified1/spv.d | 2 ++ + 10 files changed, 37 insertions(+) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 3d24085..efd329f 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -757,6 +757,7 @@ namespace Spv + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, ++ FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1169,6 +1170,7 @@ namespace Spv + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, ++ FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 4fc0ec9..1a6a490 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -16170,6 +16170,12 @@ + "capabilities" : [ "Shader" ], + "version": "1.0" + }, ++ { ++ "enumerant" : "FragmentCoverageMaskMESA", ++ "value" : 4096, ++ "capabilities" : [ "FragmentCoverageMESA" ], ++ "version" : "None" ++ }, + { + "enumerant" : "CoreIDARM", + "value" : 4160, +@@ -17309,6 +17315,13 @@ + "value" : 71, + "version" : "1.6" + }, ++ { ++ "enumerant" : "FragmentCoverageMESA", ++ "value" : 4097, ++ "capabilities" : [ "Shader" ], ++ "extensions" : [ "SPV_MESA_fragment_coverage_mask" ], ++ "version" : "None" ++ }, + { + "enumerant" : "CoreBuiltinsARM", + "value" : 4165, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 35b9aff..248e593 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -756,6 +756,7 @@ namespace Spv + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, ++ FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1168,6 +1169,7 @@ namespace Spv + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, ++ FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index a9e4998..ea4fb66 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -743,6 +743,7 @@ typedef enum SpvBuiltIn_ { + SpvBuiltInSubgroupLocalInvocationId = 41, + SpvBuiltInVertexIndex = 42, + SpvBuiltInInstanceIndex = 43, ++ SpvBuiltInFragmentCoverageMaskMESA = 4096, + SpvBuiltInCoreIDARM = 4160, + SpvBuiltInCoreCountARM = 4161, + SpvBuiltInCoreMaxIDARM = 4162, +@@ -1139,6 +1140,7 @@ typedef enum SpvCapability_ { + SpvCapabilityShaderLayer = 69, + SpvCapabilityShaderViewportIndex = 70, + SpvCapabilityUniformDecoration = 71, ++ SpvCapabilityFragmentCoverageMESA = 4097, + SpvCapabilityCoreBuiltinsARM = 4165, + SpvCapabilityTileImageColorReadAccessEXT = 4166, + SpvCapabilityTileImageDepthReadAccessEXT = 4167, +@@ -4118,6 +4120,7 @@ inline const char* SpvBuiltInToString(SpvBuiltIn value) { + case SpvBuiltInSubgroupLocalInvocationId: return "SubgroupLocalInvocationId"; + case SpvBuiltInVertexIndex: return "VertexIndex"; + case SpvBuiltInInstanceIndex: return "InstanceIndex"; ++ case SpvBuiltInFragmentCoverageMaskMESA: return "FragmentCoverageMaskMESA"; + case SpvBuiltInCoreIDARM: return "CoreIDARM"; + case SpvBuiltInCoreCountARM: return "CoreCountARM"; + case SpvBuiltInCoreMaxIDARM: return "CoreMaxIDARM"; +@@ -4316,6 +4319,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityShaderLayer: return "ShaderLayer"; + case SpvCapabilityShaderViewportIndex: return "ShaderViewportIndex"; + case SpvCapabilityUniformDecoration: return "UniformDecoration"; ++ case SpvCapabilityFragmentCoverageMESA: return "FragmentCoverageMESA"; + case SpvCapabilityCoreBuiltinsARM: return "CoreBuiltinsARM"; + case SpvCapabilityTileImageColorReadAccessEXT: return "TileImageColorReadAccessEXT"; + case SpvCapabilityTileImageDepthReadAccessEXT: return "TileImageDepthReadAccessEXT"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 6676d71..3a61c4d 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -739,6 +739,7 @@ enum BuiltIn { + BuiltInSubgroupLocalInvocationId = 41, + BuiltInVertexIndex = 42, + BuiltInInstanceIndex = 43, ++ BuiltInFragmentCoverageMaskMESA = 4096, + BuiltInCoreIDARM = 4160, + BuiltInCoreCountARM = 4161, + BuiltInCoreMaxIDARM = 4162, +@@ -1135,6 +1136,7 @@ enum Capability { + CapabilityShaderLayer = 69, + CapabilityShaderViewportIndex = 70, + CapabilityUniformDecoration = 71, ++ CapabilityFragmentCoverageMESA = 4097, + CapabilityCoreBuiltinsARM = 4165, + CapabilityTileImageColorReadAccessEXT = 4166, + CapabilityTileImageDepthReadAccessEXT = 4167, +@@ -4114,6 +4116,7 @@ inline const char* BuiltInToString(BuiltIn value) { + case BuiltInSubgroupLocalInvocationId: return "SubgroupLocalInvocationId"; + case BuiltInVertexIndex: return "VertexIndex"; + case BuiltInInstanceIndex: return "InstanceIndex"; ++ case BuiltInFragmentCoverageMaskMESA: return "FragmentCoverageMaskMESA"; + case BuiltInCoreIDARM: return "CoreIDARM"; + case BuiltInCoreCountARM: return "CoreCountARM"; + case BuiltInCoreMaxIDARM: return "CoreMaxIDARM"; +@@ -4312,6 +4315,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityShaderLayer: return "ShaderLayer"; + case CapabilityShaderViewportIndex: return "ShaderViewportIndex"; + case CapabilityUniformDecoration: return "UniformDecoration"; ++ case CapabilityFragmentCoverageMESA: return "FragmentCoverageMESA"; + case CapabilityCoreBuiltinsARM: return "CoreBuiltinsARM"; + case CapabilityTileImageColorReadAccessEXT: return "TileImageColorReadAccessEXT"; + case CapabilityTileImageDepthReadAccessEXT: return "TileImageDepthReadAccessEXT"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index e08b65b..a3c8b1c 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -739,6 +739,7 @@ enum class BuiltIn : unsigned { + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, ++ FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1135,6 +1136,7 @@ enum class Capability : unsigned { + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, ++ FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +@@ -4114,6 +4116,7 @@ inline const char* BuiltInToString(BuiltIn value) { + case BuiltIn::SubgroupLocalInvocationId: return "SubgroupLocalInvocationId"; + case BuiltIn::VertexIndex: return "VertexIndex"; + case BuiltIn::InstanceIndex: return "InstanceIndex"; ++ case BuiltIn::FragmentCoverageMaskMESA: return "FragmentCoverageMaskMESA"; + case BuiltIn::CoreIDARM: return "CoreIDARM"; + case BuiltIn::CoreCountARM: return "CoreCountARM"; + case BuiltIn::CoreMaxIDARM: return "CoreMaxIDARM"; +@@ -4312,6 +4315,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::ShaderLayer: return "ShaderLayer"; + case Capability::ShaderViewportIndex: return "ShaderViewportIndex"; + case Capability::UniformDecoration: return "UniformDecoration"; ++ case Capability::FragmentCoverageMESA: return "FragmentCoverageMESA"; + case Capability::CoreBuiltinsARM: return "CoreBuiltinsARM"; + case Capability::TileImageColorReadAccessEXT: return "TileImageColorReadAccessEXT"; + case Capability::TileImageDepthReadAccessEXT: return "TileImageDepthReadAccessEXT"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index bd3f41b..88f2605 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -765,6 +765,7 @@ + "SubgroupLocalInvocationId": 41, + "VertexIndex": 42, + "InstanceIndex": 43, ++ "FragmentCoverageMaskMESA": 4096, + "CoreIDARM": 4160, + "CoreCountARM": 4161, + "CoreMaxIDARM": 4162, +@@ -1101,6 +1102,7 @@ + "ShaderLayer": 69, + "ShaderViewportIndex": 70, + "UniformDecoration": 71, ++ "FragmentCoverageMESA": 4097, + "CoreBuiltinsARM": 4165, + "TileImageColorReadAccessEXT": 4166, + "TileImageDepthReadAccessEXT": 4167, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index 347e010..db1bfd5 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -730,6 +730,7 @@ spv = { + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, ++ FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1126,6 +1127,7 @@ spv = { + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, ++ FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index a5c118d..976e23b 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -711,6 +711,7 @@ spv = { + 'SubgroupLocalInvocationId' : 41, + 'VertexIndex' : 42, + 'InstanceIndex' : 43, ++ 'FragmentCoverageMaskMESA' : 4096, + 'CoreIDARM' : 4160, + 'CoreCountARM' : 4161, + 'CoreMaxIDARM' : 4162, +@@ -1097,6 +1098,7 @@ spv = { + 'ShaderLayer' : 69, + 'ShaderViewportIndex' : 70, + 'UniformDecoration' : 71, ++ 'FragmentCoverageMESA' : 4097, + 'CoreBuiltinsARM' : 4165, + 'TileImageColorReadAccessEXT' : 4166, + 'TileImageDepthReadAccessEXT' : 4167, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 781154a..a9093d6 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -759,6 +759,7 @@ enum BuiltIn : uint + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, ++ FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1171,6 +1172,7 @@ enum Capability : uint + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, ++ FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0004-Update-headers-for-spirv-issue-373-584.patch b/internal/rosa/package/spirv/0004-Update-headers-for-spirv-issue-373-584.patch new file mode 100644 index 00000000..f0f8b615 --- /dev/null +++ b/internal/rosa/package/spirv/0004-Update-headers-for-spirv-issue-373-584.patch @@ -0,0 +1,26 @@ +From 1a22b167081842915a1c78a0b5b5a353a23284aa Mon Sep 17 00:00:00 2001 +From: alelenv <40001162+alelenv@users.noreply.github.com> +Date: Wed, 29 Apr 2026 08:50:18 -0700 +Subject: [PATCH 04/26] Update headers for spirv issue 373 (#584) + +--- + include/spirv/unified1/spirv.core.grammar.json | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 1a6a490..c7e3cc3 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -6505,7 +6505,8 @@ + { "kind" : "IdRef", "name" : "Hit Object" }, + { "kind" : "IdRef", "name" : "Ray Query" }, + { "kind" : "IdRef", "name" : "SBT Record Index" }, +- { "kind" : "IdRef", "name" : "Hit Object Attributes" } ++ { "kind" : "IdRef", "name" : "Hit Object Attributes" }, ++ { "kind" : "IdRef", "quantifier" : "?", "name" : "Hit Kind" } + ], + "capabilities" : [ "ShaderInvocationReorderEXT" ], + "version" : "None" +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0005-Reserve-some-tokens-for-Samsung-586.patch b/internal/rosa/package/spirv/0005-Reserve-some-tokens-for-Samsung-586.patch new file mode 100644 index 00000000..06a49360 --- /dev/null +++ b/internal/rosa/package/spirv/0005-Reserve-some-tokens-for-Samsung-586.patch @@ -0,0 +1,32 @@ +From 53b334f4a5f18fb1f2d367baeba8b43e2eb0b62b Mon Sep 17 00:00:00 2001 +From: Matthew Moulton <30711895+mmoult@users.noreply.github.com> +Date: Wed, 29 Apr 2026 22:25:01 +0000 +Subject: [PATCH 05/26] Reserve some tokens for Samsung (#586) + +--- + include/spirv/spir-v.xml | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml +index 15eeb4d..3b3cfb3 100644 +--- a/include/spirv/spir-v.xml ++++ b/include/spirv/spir-v.xml +@@ -179,13 +179,14 @@ + <ids type="enumerant" start="6784" end="6911" vendor="Intel" comment="Contact mariusz.merecki@intel.com"/> + <ids type="enumerant" start="6912" end="6975" vendor="Valve" comment="Contact michael.blumenkrantz@gmail.com"/> + <ids type="enumerant" start="6976" end="7039" vendor="Broadcom" comment="Contact gleese@broadcom.com"/> ++ <ids type="enumerant" start="7040" end="7103" vendor="Samsung" comment="Contact r.potter@samsung.com"/> + <!-- Enumerants to reserve for future use. To get a block, allocate + multiples of 64 starting at the lowest available point in this + block and add a corresponding <ids> tag immediately above. Make + sure to fill in the vendor attribute, and preferably add a contact + person/address in a comment attribute. --> + <!-- Example new block: <ids type="enumerant" start="XXXX" end="XXXX+64n-1" vendor="Add vendor" comment="Contact TBD"/> --> +- <ids type="enumerant" start="7040" end="4294967295" comment="Enumerant range reservable for future use by vendors"/> ++ <ids type="enumerant" start="7104" end="4294967295" comment="Enumerant range reservable for future use by vendors"/> + <!-- End reservations of enumerants --> + + +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0006-Fix-OpCompositeConstructContinuedINTEL-operands-587.patch b/internal/rosa/package/spirv/0006-Fix-OpCompositeConstructContinuedINTEL-operands-587.patch new file mode 100644 index 00000000..23378a30 --- /dev/null +++ b/internal/rosa/package/spirv/0006-Fix-OpCompositeConstructContinuedINTEL-operands-587.patch @@ -0,0 +1,74 @@ +From 126038020c2bd47efaa942ccc364ca5353ffccde Mon Sep 17 00:00:00 2001 +From: Arseniy Obolenskiy <gooddoog@student.su> +Date: Thu, 30 Apr 2026 22:51:58 +0200 +Subject: [PATCH 06/26] Fix OpCompositeConstructContinuedINTEL operands (#587) + +* Fix OpCompositeConstructContinuedINTEL operands + +Remove IdResultType and IdResult from OpCompositeConstructContinuedINTEL + +This instruction is a continuation that supplies additional constituents to a preceding OpCompositeConstruct and does not produce its own result + +* Update headers +--- + include/spirv/unified1/spirv.core.grammar.json | 2 -- + include/spirv/unified1/spirv.h | 2 +- + include/spirv/unified1/spirv.hpp | 2 +- + include/spirv/unified1/spirv.hpp11 | 2 +- + 4 files changed, 3 insertions(+), 5 deletions(-) + +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index c7e3cc3..2ca9fe4 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -11223,8 +11223,6 @@ + "class" : "Composite", + "opcode" : 6096, + "operands" : [ +- { "kind" : "IdResultType" }, +- { "kind" : "IdResult" }, + { "kind" : "IdRef", "quantifier" : "*", "name" : "Constituents" } + ], + "capabilities" : [ "LongCompositesINTEL" ], +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index ea4fb66..169cb06 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -3489,7 +3489,7 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy + case SpvOpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; +- case SpvOpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; ++ case SpvOpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 3a61c4d..c159586 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -3485,7 +3485,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; +- case OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; ++ case OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; + case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index a3c8b1c..189dbbc 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -3485,7 +3485,7 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case Op::OpTypeStructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpSpecConstantCompositeContinuedINTEL: *hasResult = false; *hasResultType = false; break; +- case Op::OpCompositeConstructContinuedINTEL: *hasResult = true; *hasResultType = true; break; ++ case Op::OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0007-Update-spirv.core.grammar.json-revision-593.patch b/internal/rosa/package/spirv/0007-Update-spirv.core.grammar.json-revision-593.patch new file mode 100644 index 00000000..08f77336 --- /dev/null +++ b/internal/rosa/package/spirv/0007-Update-spirv.core.grammar.json-revision-593.patch @@ -0,0 +1,25 @@ +From 1f2dd1627ae782fa999b6ed86514c6a905438e3c Mon Sep 17 00:00:00 2001 +From: Spencer Fricke <115671160+spencer-lunarg@users.noreply.github.com> +Date: Tue, 5 May 2026 12:29:58 -0400 +Subject: [PATCH 07/26] Update spirv.core.grammar.json revision (#593) + +--- + include/spirv/unified1/spirv.core.grammar.json | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 2ca9fe4..bd716cb 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -11,7 +11,7 @@ + "magic_number" : "0x07230203", + "major_version" : 1, + "minor_version" : 6, +- "revision" : 4, ++ "revision" : 7, + "instruction_printing_class" : [ + { + "tag" : "@exclude" +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0008-Reserve-ImageOperand-17-for-Google-589.patch b/internal/rosa/package/spirv/0008-Reserve-ImageOperand-17-for-Google-589.patch new file mode 100644 index 00000000..657d3ddf --- /dev/null +++ b/internal/rosa/package/spirv/0008-Reserve-ImageOperand-17-for-Google-589.patch @@ -0,0 +1,26 @@ +From 58006c901d1d5c37dece6b6610e9af87fa951375 Mon Sep 17 00:00:00 2001 +From: Shahbaz Youssefi <syoussefi@chromium.org> +Date: Thu, 7 May 2026 21:05:26 -0400 +Subject: [PATCH 08/26] Reserve ImageOperand 17 for Google (#589) + +--- + include/spirv/spir-v.xml | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml +index 3b3cfb3..69a2c2a 100644 +--- a/include/spirv/spir-v.xml ++++ b/include/spirv/spir-v.xml +@@ -290,7 +290,8 @@ + <!-- Reserved image operand bits --> + <ids type="ImageOperand" start="0" end="15" vendor="Khronos" comment="Reserved ImageOperand bits, not available to vendors - see the SPIR-V Specification"/> + <ids type="ImageOperand" start="16" end="16" vendor="Nvidia" comment="Contact pmistry@nvidia.com"/> +- <ids type="ImageOperand" start="17" end="30" comment="Unreserved bits reservable for use by vendors"/> ++ <ids type="ImageOperand" start="17" end="17" vendor="Google" comment="Contact syoussefi@google.com"/> ++ <ids type="ImageOperand" start="18" end="30" comment="Unreserved bits reservable for use by vendors"/> + <ids type="ImageOperand" start="31" end="31" vendor="Khronos" comment="Reserved ImageOperand bit, not available to vendors"/> + + </registry> +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0009-Fix-OpReadPipeBlockingINTEL-OpWritePipeBlockingINTEL.patch b/internal/rosa/package/spirv/0009-Fix-OpReadPipeBlockingINTEL-OpWritePipeBlockingINTEL.patch new file mode 100644 index 00000000..7fe6dc2c --- /dev/null +++ b/internal/rosa/package/spirv/0009-Fix-OpReadPipeBlockingINTEL-OpWritePipeBlockingINTEL.patch @@ -0,0 +1,88 @@ +From 98c842bd561ac67c5ff98d599c8c960ba9edb7fd Mon Sep 17 00:00:00 2001 +From: Arseniy Obolenskiy <gooddoog@student.su> +Date: Mon, 11 May 2026 13:11:51 +0200 +Subject: [PATCH 09/26] Fix OpReadPipeBlockingINTEL/OpWritePipeBlockingINTEL + operands (#588) + +Per the SPV_INTEL_blocking_pipes spec, these instructions do not produce a result, but have Pipe and Pointer id arguments instead +--- + include/spirv/unified1/spirv.core.grammar.json | 8 ++++---- + include/spirv/unified1/spirv.h | 4 ++-- + include/spirv/unified1/spirv.hpp | 4 ++-- + include/spirv/unified1/spirv.hpp11 | 4 ++-- + 4 files changed, 10 insertions(+), 10 deletions(-) + +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index bd716cb..d8d36df 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -10803,8 +10803,8 @@ + "aliases" : [ "OpReadPipeBlockingINTEL" ], + "opcode" : 5946, + "operands" : [ +- { "kind" : "IdResultType" }, +- { "kind" : "IdResult" }, ++ { "kind" : "IdRef", "name" : "Pipe" }, ++ { "kind" : "IdRef", "name" : "Pointer" }, + { "kind" : "IdRef", "name" : "Packet Size" }, + { "kind" : "IdRef", "name" : "Packet Alignment" } + ], +@@ -10817,8 +10817,8 @@ + "aliases" : [ "OpWritePipeBlockingINTEL" ], + "opcode" : 5947, + "operands" : [ +- { "kind" : "IdResultType" }, +- { "kind" : "IdResult" }, ++ { "kind" : "IdRef", "name" : "Pipe" }, ++ { "kind" : "IdRef", "name" : "Pointer" }, + { "kind" : "IdRef", "name" : "Packet Size" }, + { "kind" : "IdRef", "name" : "Packet Alignment" } + ], +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 169cb06..1759d89 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -3464,8 +3464,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy + case SpvOpFixedExpALTERA: *hasResult = true; *hasResultType = true; break; + case SpvOpPtrCastToCrossWorkgroupALTERA: *hasResult = true; *hasResultType = true; break; + case SpvOpCrossWorkgroupCastToPtrALTERA: *hasResult = true; *hasResultType = true; break; +- case SpvOpReadPipeBlockingALTERA: *hasResult = true; *hasResultType = true; break; +- case SpvOpWritePipeBlockingALTERA: *hasResult = true; *hasResultType = true; break; ++ case SpvOpReadPipeBlockingALTERA: *hasResult = false; *hasResultType = false; break; ++ case SpvOpWritePipeBlockingALTERA: *hasResult = false; *hasResultType = false; break; + case SpvOpFPGARegALTERA: *hasResult = true; *hasResultType = true; break; + case SpvOpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break; + case SpvOpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index c159586..e6cc26c 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -3460,8 +3460,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case OpFixedExpALTERA: *hasResult = true; *hasResultType = true; break; + case OpPtrCastToCrossWorkgroupALTERA: *hasResult = true; *hasResultType = true; break; + case OpCrossWorkgroupCastToPtrALTERA: *hasResult = true; *hasResultType = true; break; +- case OpReadPipeBlockingALTERA: *hasResult = true; *hasResultType = true; break; +- case OpWritePipeBlockingALTERA: *hasResult = true; *hasResultType = true; break; ++ case OpReadPipeBlockingALTERA: *hasResult = false; *hasResultType = false; break; ++ case OpWritePipeBlockingALTERA: *hasResult = false; *hasResultType = false; break; + case OpFPGARegALTERA: *hasResult = true; *hasResultType = true; break; + case OpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break; + case OpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index 189dbbc..c841190 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -3460,8 +3460,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case Op::OpFixedExpALTERA: *hasResult = true; *hasResultType = true; break; + case Op::OpPtrCastToCrossWorkgroupALTERA: *hasResult = true; *hasResultType = true; break; + case Op::OpCrossWorkgroupCastToPtrALTERA: *hasResult = true; *hasResultType = true; break; +- case Op::OpReadPipeBlockingALTERA: *hasResult = true; *hasResultType = true; break; +- case Op::OpWritePipeBlockingALTERA: *hasResult = true; *hasResultType = true; break; ++ case Op::OpReadPipeBlockingALTERA: *hasResult = false; *hasResultType = false; break; ++ case Op::OpWritePipeBlockingALTERA: *hasResult = false; *hasResultType = false; break; + case Op::OpFPGARegALTERA: *hasResult = true; *hasResultType = true; break; + case Op::OpRayQueryGetRayTMinKHR: *hasResult = true; *hasResultType = true; break; + case Op::OpRayQueryGetRayFlagsKHR: *hasResult = true; *hasResultType = true; break; +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0010-Add-SPV_AMD_weak_linkage-extension-583.patch b/internal/rosa/package/spirv/0010-Add-SPV_AMD_weak_linkage-extension-583.patch new file mode 100644 index 00000000..5e25de20 --- /dev/null +++ b/internal/rosa/package/spirv/0010-Add-SPV_AMD_weak_linkage-extension-583.patch @@ -0,0 +1,283 @@ +From 5c50cbd25a40f8b60e44a2ccc2f1ba3c9e0d0299 Mon Sep 17 00:00:00 2001 +From: Dmitry Sidorov <dsidorov@amd.com> +Date: Wed, 13 May 2026 15:01:58 +0200 +Subject: [PATCH 10/26] Add SPV_AMD_weak_linkage extension (#583) + +Spec is available here KhronosGroup/SPIRV-Registry#401 +--- + include/spirv/unified1/spirv.bf | 2 ++ + include/spirv/unified1/spirv.core.grammar.json | 13 +++++++++++++ + include/spirv/unified1/spirv.cs | 2 ++ + include/spirv/unified1/spirv.h | 4 ++++ + include/spirv/unified1/spirv.hpp | 4 ++++ + include/spirv/unified1/spirv.hpp11 | 4 ++++ + include/spirv/unified1/spirv.json | 4 +++- + include/spirv/unified1/spirv.lua | 2 ++ + include/spirv/unified1/spirv.py | 2 ++ + include/spirv/unified1/spv.d | 2 ++ + 10 files changed, 38 insertions(+), 1 deletion(-) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index efd329f..8d0bc34 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -485,6 +485,7 @@ namespace Spv + Export = 0, + Import = 1, + LinkOnceODR = 2, ++ WeakAMD = 3, + Max = 0x7fffffff, + } + +@@ -1238,6 +1239,7 @@ namespace Spv + DescriptorHeapEXT = 5128, + ConstantDataKHR = 5146, + PoisonFreezeKHR = 5156, ++ WeakLinkageAMD = 5181, + SampleMaskOverrideCoverageNV = 5249, + GeometryShaderPassthroughNV = 5251, + ShaderViewportIndexLayerEXT = 5254, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index d8d36df..c84dc2d 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -14595,6 +14595,12 @@ + "capabilities" : [ "Linkage" ], + "extensions" : [ "SPV_KHR_linkonce_odr" ], + "version" : "None" ++ }, ++ { ++ "enumerant" : "WeakAMD", ++ "value" : 3, ++ "capabilities" : [ "WeakLinkageAMD" ], ++ "version" : "None" + } + ] + }, +@@ -17744,6 +17750,13 @@ + "provisional" : true, + "version" : "None" + }, ++ { ++ "enumerant" : "WeakLinkageAMD", ++ "value" : 5181, ++ "capabilities" : [ "Linkage" ], ++ "extensions" : [ "SPV_AMD_weak_linkage" ], ++ "version" : "None" ++ }, + { + "enumerant" : "SampleMaskOverrideCoverageNV", + "value" : 5249, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 248e593..b0a8f1e 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -484,6 +484,7 @@ namespace Spv + Export = 0, + Import = 1, + LinkOnceODR = 2, ++ WeakAMD = 3, + Max = 0x7fffffff, + } + +@@ -1237,6 +1238,7 @@ namespace Spv + DescriptorHeapEXT = 5128, + ConstantDataKHR = 5146, + PoisonFreezeKHR = 5156, ++ WeakLinkageAMD = 5181, + SampleMaskOverrideCoverageNV = 5249, + GeometryShaderPassthroughNV = 5251, + ShaderViewportIndexLayerEXT = 5254, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 1759d89..4f76b90 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -475,6 +475,7 @@ typedef enum SpvLinkageType_ { + SpvLinkageTypeExport = 0, + SpvLinkageTypeImport = 1, + SpvLinkageTypeLinkOnceODR = 2, ++ SpvLinkageTypeWeakAMD = 3, + SpvLinkageTypeMax = 0x7fffffff, + } SpvLinkageType; + +@@ -1208,6 +1209,7 @@ typedef enum SpvCapability_ { + SpvCapabilityDescriptorHeapEXT = 5128, + SpvCapabilityConstantDataKHR = 5146, + SpvCapabilityPoisonFreezeKHR = 5156, ++ SpvCapabilityWeakLinkageAMD = 5181, + SpvCapabilitySampleMaskOverrideCoverageNV = 5249, + SpvCapabilityGeometryShaderPassthroughNV = 5251, + SpvCapabilityShaderViewportIndexLayerEXT = 5254, +@@ -3893,6 +3895,7 @@ inline const char* SpvLinkageTypeToString(SpvLinkageType value) { + case SpvLinkageTypeExport: return "Export"; + case SpvLinkageTypeImport: return "Import"; + case SpvLinkageTypeLinkOnceODR: return "LinkOnceODR"; ++ case SpvLinkageTypeWeakAMD: return "WeakAMD"; + default: return "Unknown"; + } + } +@@ -4385,6 +4388,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityDescriptorHeapEXT: return "DescriptorHeapEXT"; + case SpvCapabilityConstantDataKHR: return "ConstantDataKHR"; + case SpvCapabilityPoisonFreezeKHR: return "PoisonFreezeKHR"; ++ case SpvCapabilityWeakLinkageAMD: return "WeakLinkageAMD"; + case SpvCapabilitySampleMaskOverrideCoverageNV: return "SampleMaskOverrideCoverageNV"; + case SpvCapabilityGeometryShaderPassthroughNV: return "GeometryShaderPassthroughNV"; + case SpvCapabilityShaderViewportIndexLayerEXT: return "ShaderViewportIndexLayerEXT"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index e6cc26c..fd64eb7 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -471,6 +471,7 @@ enum LinkageType { + LinkageTypeExport = 0, + LinkageTypeImport = 1, + LinkageTypeLinkOnceODR = 2, ++ LinkageTypeWeakAMD = 3, + LinkageTypeMax = 0x7fffffff, + }; + +@@ -1204,6 +1205,7 @@ enum Capability { + CapabilityDescriptorHeapEXT = 5128, + CapabilityConstantDataKHR = 5146, + CapabilityPoisonFreezeKHR = 5156, ++ CapabilityWeakLinkageAMD = 5181, + CapabilitySampleMaskOverrideCoverageNV = 5249, + CapabilityGeometryShaderPassthroughNV = 5251, + CapabilityShaderViewportIndexLayerEXT = 5254, +@@ -3889,6 +3891,7 @@ inline const char* LinkageTypeToString(LinkageType value) { + case LinkageTypeExport: return "Export"; + case LinkageTypeImport: return "Import"; + case LinkageTypeLinkOnceODR: return "LinkOnceODR"; ++ case LinkageTypeWeakAMD: return "WeakAMD"; + default: return "Unknown"; + } + } +@@ -4381,6 +4384,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityDescriptorHeapEXT: return "DescriptorHeapEXT"; + case CapabilityConstantDataKHR: return "ConstantDataKHR"; + case CapabilityPoisonFreezeKHR: return "PoisonFreezeKHR"; ++ case CapabilityWeakLinkageAMD: return "WeakLinkageAMD"; + case CapabilitySampleMaskOverrideCoverageNV: return "SampleMaskOverrideCoverageNV"; + case CapabilityGeometryShaderPassthroughNV: return "GeometryShaderPassthroughNV"; + case CapabilityShaderViewportIndexLayerEXT: return "ShaderViewportIndexLayerEXT"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index c841190..4e626c9 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -471,6 +471,7 @@ enum class LinkageType : unsigned { + Export = 0, + Import = 1, + LinkOnceODR = 2, ++ WeakAMD = 3, + Max = 0x7fffffff, + }; + +@@ -1204,6 +1205,7 @@ enum class Capability : unsigned { + DescriptorHeapEXT = 5128, + ConstantDataKHR = 5146, + PoisonFreezeKHR = 5156, ++ WeakLinkageAMD = 5181, + SampleMaskOverrideCoverageNV = 5249, + GeometryShaderPassthroughNV = 5251, + ShaderViewportIndexLayerEXT = 5254, +@@ -3889,6 +3891,7 @@ inline const char* LinkageTypeToString(LinkageType value) { + case LinkageType::Export: return "Export"; + case LinkageType::Import: return "Import"; + case LinkageType::LinkOnceODR: return "LinkOnceODR"; ++ case LinkageType::WeakAMD: return "WeakAMD"; + default: return "Unknown"; + } + } +@@ -4381,6 +4384,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::DescriptorHeapEXT: return "DescriptorHeapEXT"; + case Capability::ConstantDataKHR: return "ConstantDataKHR"; + case Capability::PoisonFreezeKHR: return "PoisonFreezeKHR"; ++ case Capability::WeakLinkageAMD: return "WeakLinkageAMD"; + case Capability::SampleMaskOverrideCoverageNV: return "SampleMaskOverrideCoverageNV"; + case Capability::GeometryShaderPassthroughNV: return "GeometryShaderPassthroughNV"; + case Capability::ShaderViewportIndexLayerEXT: return "ShaderViewportIndexLayerEXT"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 88f2605..135663c 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -484,7 +484,8 @@ + { + "Export": 0, + "Import": 1, +- "LinkOnceODR": 2 ++ "LinkOnceODR": 2, ++ "WeakAMD": 3 + } + }, + { +@@ -1170,6 +1171,7 @@ + "DescriptorHeapEXT": 5128, + "ConstantDataKHR": 5146, + "PoisonFreezeKHR": 5156, ++ "WeakLinkageAMD": 5181, + "SampleMaskOverrideCoverageNV": 5249, + "GeometryShaderPassthroughNV": 5251, + "ShaderViewportIndexLayerEXT": 5254, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index db1bfd5..8cbe093 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -462,6 +462,7 @@ spv = { + Export = 0, + Import = 1, + LinkOnceODR = 2, ++ WeakAMD = 3, + Max = 0x7fffffff, + }, + +@@ -1195,6 +1196,7 @@ spv = { + DescriptorHeapEXT = 5128, + ConstantDataKHR = 5146, + PoisonFreezeKHR = 5156, ++ WeakLinkageAMD = 5181, + SampleMaskOverrideCoverageNV = 5249, + GeometryShaderPassthroughNV = 5251, + ShaderViewportIndexLayerEXT = 5254, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index 976e23b..bb65ae9 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -447,6 +447,7 @@ spv = { + 'Export' : 0, + 'Import' : 1, + 'LinkOnceODR' : 2, ++ 'WeakAMD' : 3, + }, + + 'AccessQualifier' : { +@@ -1166,6 +1167,7 @@ spv = { + 'DescriptorHeapEXT' : 5128, + 'ConstantDataKHR' : 5146, + 'PoisonFreezeKHR' : 5156, ++ 'WeakLinkageAMD' : 5181, + 'SampleMaskOverrideCoverageNV' : 5249, + 'GeometryShaderPassthroughNV' : 5251, + 'ShaderViewportIndexLayerEXT' : 5254, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index a9093d6..8d31fee 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -487,6 +487,7 @@ enum LinkageType : uint + Export = 0, + Import = 1, + LinkOnceODR = 2, ++ WeakAMD = 3, + Max = 0x7fffffff, + } + +@@ -1240,6 +1241,7 @@ enum Capability : uint + DescriptorHeapEXT = 5128, + ConstantDataKHR = 5146, + PoisonFreezeKHR = 5156, ++ WeakLinkageAMD = 5181, + SampleMaskOverrideCoverageNV = 5249, + GeometryShaderPassthroughNV = 5251, + ShaderViewportIndexLayerEXT = 5254, +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0011-Add-SPV_KHR_opacity_micromap-599.patch b/internal/rosa/package/spirv/0011-Add-SPV_KHR_opacity_micromap-599.patch new file mode 100644 index 00000000..ceea6134 --- /dev/null +++ b/internal/rosa/package/spirv/0011-Add-SPV_KHR_opacity_micromap-599.patch @@ -0,0 +1,520 @@ +From 62d3e8314d2c4f26de24ca508bca2070f3d254aa Mon Sep 17 00:00:00 2001 +From: Spencer Fricke <115671160+spencer-lunarg@users.noreply.github.com> +Date: Wed, 13 May 2026 11:47:28 -0400 +Subject: [PATCH 11/26] Add SPV_KHR_opacity_micromap (#599) + +--- + include/spirv/unified1/spirv.bf | 5 ++++ + .../spirv/unified1/spirv.core.grammar.json | 26 ++++++++++++++++--- + include/spirv/unified1/spirv.cs | 5 ++++ + include/spirv/unified1/spirv.h | 7 +++++ + include/spirv/unified1/spirv.hpp | 7 +++++ + include/spirv/unified1/spirv.hpp11 | 7 +++++ + include/spirv/unified1/spirv.json | 6 ++++- + include/spirv/unified1/spirv.lua | 5 ++++ + include/spirv/unified1/spirv.py | 5 ++++ + include/spirv/unified1/spv.d | 5 ++++ + 10 files changed, 73 insertions(+), 5 deletions(-) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 8d0bc34..a512a3e 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -206,6 +206,7 @@ namespace Spv + SchedulerTargetFmaxMhzINTEL = 5903, + MaximallyReconvergesKHR = 6023, + FPFastMathDefault = 6028, ++ OpacityMicromapIdKHR = 6031, + StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, + NamedBarrierCountINTEL = 6417, +@@ -1304,6 +1305,7 @@ namespace Spv + DemoteToHelperInvocationEXT = 5379, + DisplacementMicromapNV = 5380, + RayTracingOpacityMicromapEXT = 5381, ++ RayTracingOpacityMicromapKHR = 5381, + ShaderInvocationReorderNV = 5383, + ShaderInvocationReorderEXT = 5388, + BindlessTextureNV = 5390, +@@ -1398,6 +1400,7 @@ namespace Spv + GroupNonUniformRotateKHR = 6026, + FloatControls2 = 6029, + FMAKHR = 6030, ++ RayTracingOpacityMicromapExecutionModeKHR = 6032, + AtomicFloat32AddEXT = 6033, + AtomicFloat64AddEXT = 6034, + LongCompositesINTEL = 6089, +@@ -1459,6 +1462,7 @@ namespace Spv + SkipTrianglesKHR = 8, + SkipAABBsKHR = 9, + ForceOpacityMicromap2StateEXT = 10, ++ ForceOpacityMicromap2StateKHR = 10, + Max = 0x7fffffff, + } + +@@ -1477,6 +1481,7 @@ namespace Spv + SkipTrianglesKHR = 0x00000100, + SkipAABBsKHR = 0x00000200, + ForceOpacityMicromap2StateEXT = 0x00000400, ++ ForceOpacityMicromap2StateKHR = 0x00000400, + } + + [AllowDuplicates, CRepr] public enum RayQueryIntersection +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index c84dc2d..32a350a 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -12549,9 +12549,10 @@ + "version" : "None" + }, + { +- "enumerant" : "ForceOpacityMicromap2StateEXT", ++ "enumerant" : "ForceOpacityMicromap2StateKHR", ++ "aliases" : [ "ForceOpacityMicromap2StateEXT" ], + "value" : "0x0400", +- "capabilities" : [ "RayTracingOpacityMicromapEXT" ], ++ "capabilities" : [ "RayTracingOpacityMicromapKHR" ], + "version" : "None" + } + ] +@@ -13576,6 +13577,15 @@ + "capabilities" : [ "FloatControls2" ], + "version" : "None" + }, ++ { ++ "enumerant" : "OpacityMicromapIdKHR", ++ "value" : 6031, ++ "capabilities" : [ "RayTracingOpacityMicromapExecutionModeKHR" ], ++ "parameters" : [ ++ { "kind" : "IdRef", "name" : "Enable" } ++ ], ++ "version" : "None" ++ }, + { + "enumerant" : "StreamingInterfaceINTEL", + "value" : 6154, +@@ -18062,10 +18072,11 @@ + "version" : "None" + }, + { +- "enumerant" : "RayTracingOpacityMicromapEXT", ++ "enumerant" : "RayTracingOpacityMicromapKHR", ++ "aliases" : ["RayTracingOpacityMicromapEXT"], + "value" : 5381, + "capabilities" : [ "Shader" ], +- "extensions" : [ "SPV_EXT_opacity_micromap" ], ++ "extensions" : ["SPV_KHR_opacity_micromap", "SPV_EXT_opacity_micromap"], + "version" : "None" + }, + { +@@ -18542,6 +18553,13 @@ + "extensions" : [ "SPV_KHR_fma" ], + "version" : "None" + }, ++ { ++ "enumerant" : "RayTracingOpacityMicromapExecutionModeKHR", ++ "value" : 6032, ++ "capabilities" : [ "Shader" ], ++ "extensions" : [ "SPV_KHR_opacity_micromap" ], ++ "version" : "None" ++ }, + { + "enumerant" : "AtomicFloat32AddEXT", + "value" : 6033, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index b0a8f1e..4d33ffa 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -205,6 +205,7 @@ namespace Spv + SchedulerTargetFmaxMhzINTEL = 5903, + MaximallyReconvergesKHR = 6023, + FPFastMathDefault = 6028, ++ OpacityMicromapIdKHR = 6031, + StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, + NamedBarrierCountINTEL = 6417, +@@ -1303,6 +1304,7 @@ namespace Spv + DemoteToHelperInvocationEXT = 5379, + DisplacementMicromapNV = 5380, + RayTracingOpacityMicromapEXT = 5381, ++ RayTracingOpacityMicromapKHR = 5381, + ShaderInvocationReorderNV = 5383, + ShaderInvocationReorderEXT = 5388, + BindlessTextureNV = 5390, +@@ -1397,6 +1399,7 @@ namespace Spv + GroupNonUniformRotateKHR = 6026, + FloatControls2 = 6029, + FMAKHR = 6030, ++ RayTracingOpacityMicromapExecutionModeKHR = 6032, + AtomicFloat32AddEXT = 6033, + AtomicFloat64AddEXT = 6034, + LongCompositesINTEL = 6089, +@@ -1458,6 +1461,7 @@ namespace Spv + SkipTrianglesKHR = 8, + SkipAABBsKHR = 9, + ForceOpacityMicromap2StateEXT = 10, ++ ForceOpacityMicromap2StateKHR = 10, + Max = 0x7fffffff, + } + +@@ -1476,6 +1480,7 @@ namespace Spv + SkipTrianglesKHR = 0x00000100, + SkipAABBsKHR = 0x00000200, + ForceOpacityMicromap2StateEXT = 0x00000400, ++ ForceOpacityMicromap2StateKHR = 0x00000400, + } + + public enum RayQueryIntersection +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 4f76b90..d9dedc0 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -209,6 +209,7 @@ typedef enum SpvExecutionMode_ { + SpvExecutionModeSchedulerTargetFmaxMhzINTEL = 5903, + SpvExecutionModeMaximallyReconvergesKHR = 6023, + SpvExecutionModeFPFastMathDefault = 6028, ++ SpvExecutionModeOpacityMicromapIdKHR = 6031, + SpvExecutionModeStreamingInterfaceINTEL = 6154, + SpvExecutionModeRegisterMapInterfaceINTEL = 6160, + SpvExecutionModeNamedBarrierCountINTEL = 6417, +@@ -1274,6 +1275,7 @@ typedef enum SpvCapability_ { + SpvCapabilityDemoteToHelperInvocationEXT = 5379, + SpvCapabilityDisplacementMicromapNV = 5380, + SpvCapabilityRayTracingOpacityMicromapEXT = 5381, ++ SpvCapabilityRayTracingOpacityMicromapKHR = 5381, + SpvCapabilityShaderInvocationReorderNV = 5383, + SpvCapabilityShaderInvocationReorderEXT = 5388, + SpvCapabilityBindlessTextureNV = 5390, +@@ -1368,6 +1370,7 @@ typedef enum SpvCapability_ { + SpvCapabilityGroupNonUniformRotateKHR = 6026, + SpvCapabilityFloatControls2 = 6029, + SpvCapabilityFMAKHR = 6030, ++ SpvCapabilityRayTracingOpacityMicromapExecutionModeKHR = 6032, + SpvCapabilityAtomicFloat32AddEXT = 6033, + SpvCapabilityAtomicFloat64AddEXT = 6034, + SpvCapabilityLongCompositesINTEL = 6089, +@@ -1428,6 +1431,7 @@ typedef enum SpvRayFlagsShift_ { + SpvRayFlagsSkipTrianglesKHRShift = 8, + SpvRayFlagsSkipAABBsKHRShift = 9, + SpvRayFlagsForceOpacityMicromap2StateEXTShift = 10, ++ SpvRayFlagsForceOpacityMicromap2StateKHRShift = 10, + SpvRayFlagsMax = 0x7fffffff, + } SpvRayFlagsShift; + +@@ -1445,6 +1449,7 @@ typedef enum SpvRayFlagsMask_ { + SpvRayFlagsSkipTrianglesKHRMask = 0x00000100, + SpvRayFlagsSkipAABBsKHRMask = 0x00000200, + SpvRayFlagsForceOpacityMicromap2StateEXTMask = 0x00000400, ++ SpvRayFlagsForceOpacityMicromap2StateKHRMask = 0x00000400, + } SpvRayFlagsMask; + + typedef enum SpvRayQueryIntersection_ { +@@ -3696,6 +3701,7 @@ inline const char* SpvExecutionModeToString(SpvExecutionMode value) { + case SpvExecutionModeSchedulerTargetFmaxMhzINTEL: return "SchedulerTargetFmaxMhzINTEL"; + case SpvExecutionModeMaximallyReconvergesKHR: return "MaximallyReconvergesKHR"; + case SpvExecutionModeFPFastMathDefault: return "FPFastMathDefault"; ++ case SpvExecutionModeOpacityMicromapIdKHR: return "OpacityMicromapIdKHR"; + case SpvExecutionModeStreamingInterfaceINTEL: return "StreamingInterfaceINTEL"; + case SpvExecutionModeRegisterMapInterfaceINTEL: return "RegisterMapInterfaceINTEL"; + case SpvExecutionModeNamedBarrierCountINTEL: return "NamedBarrierCountINTEL"; +@@ -4505,6 +4511,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityGroupNonUniformRotateKHR: return "GroupNonUniformRotateKHR"; + case SpvCapabilityFloatControls2: return "FloatControls2"; + case SpvCapabilityFMAKHR: return "FMAKHR"; ++ case SpvCapabilityRayTracingOpacityMicromapExecutionModeKHR: return "RayTracingOpacityMicromapExecutionModeKHR"; + case SpvCapabilityAtomicFloat32AddEXT: return "AtomicFloat32AddEXT"; + case SpvCapabilityAtomicFloat64AddEXT: return "AtomicFloat64AddEXT"; + case SpvCapabilityLongCompositesINTEL: return "LongCompositesINTEL"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index fd64eb7..d0a1606 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -205,6 +205,7 @@ enum ExecutionMode { + ExecutionModeSchedulerTargetFmaxMhzINTEL = 5903, + ExecutionModeMaximallyReconvergesKHR = 6023, + ExecutionModeFPFastMathDefault = 6028, ++ ExecutionModeOpacityMicromapIdKHR = 6031, + ExecutionModeStreamingInterfaceINTEL = 6154, + ExecutionModeRegisterMapInterfaceINTEL = 6160, + ExecutionModeNamedBarrierCountINTEL = 6417, +@@ -1270,6 +1271,7 @@ enum Capability { + CapabilityDemoteToHelperInvocationEXT = 5379, + CapabilityDisplacementMicromapNV = 5380, + CapabilityRayTracingOpacityMicromapEXT = 5381, ++ CapabilityRayTracingOpacityMicromapKHR = 5381, + CapabilityShaderInvocationReorderNV = 5383, + CapabilityShaderInvocationReorderEXT = 5388, + CapabilityBindlessTextureNV = 5390, +@@ -1364,6 +1366,7 @@ enum Capability { + CapabilityGroupNonUniformRotateKHR = 6026, + CapabilityFloatControls2 = 6029, + CapabilityFMAKHR = 6030, ++ CapabilityRayTracingOpacityMicromapExecutionModeKHR = 6032, + CapabilityAtomicFloat32AddEXT = 6033, + CapabilityAtomicFloat64AddEXT = 6034, + CapabilityLongCompositesINTEL = 6089, +@@ -1424,6 +1427,7 @@ enum RayFlagsShift { + RayFlagsSkipTrianglesKHRShift = 8, + RayFlagsSkipAABBsKHRShift = 9, + RayFlagsForceOpacityMicromap2StateEXTShift = 10, ++ RayFlagsForceOpacityMicromap2StateKHRShift = 10, + RayFlagsMax = 0x7fffffff, + }; + +@@ -1441,6 +1445,7 @@ enum RayFlagsMask { + RayFlagsSkipTrianglesKHRMask = 0x00000100, + RayFlagsSkipAABBsKHRMask = 0x00000200, + RayFlagsForceOpacityMicromap2StateEXTMask = 0x00000400, ++ RayFlagsForceOpacityMicromap2StateKHRMask = 0x00000400, + }; + + enum RayQueryIntersection { +@@ -3692,6 +3697,7 @@ inline const char* ExecutionModeToString(ExecutionMode value) { + case ExecutionModeSchedulerTargetFmaxMhzINTEL: return "SchedulerTargetFmaxMhzINTEL"; + case ExecutionModeMaximallyReconvergesKHR: return "MaximallyReconvergesKHR"; + case ExecutionModeFPFastMathDefault: return "FPFastMathDefault"; ++ case ExecutionModeOpacityMicromapIdKHR: return "OpacityMicromapIdKHR"; + case ExecutionModeStreamingInterfaceINTEL: return "StreamingInterfaceINTEL"; + case ExecutionModeRegisterMapInterfaceINTEL: return "RegisterMapInterfaceINTEL"; + case ExecutionModeNamedBarrierCountINTEL: return "NamedBarrierCountINTEL"; +@@ -4501,6 +4507,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityGroupNonUniformRotateKHR: return "GroupNonUniformRotateKHR"; + case CapabilityFloatControls2: return "FloatControls2"; + case CapabilityFMAKHR: return "FMAKHR"; ++ case CapabilityRayTracingOpacityMicromapExecutionModeKHR: return "RayTracingOpacityMicromapExecutionModeKHR"; + case CapabilityAtomicFloat32AddEXT: return "AtomicFloat32AddEXT"; + case CapabilityAtomicFloat64AddEXT: return "AtomicFloat64AddEXT"; + case CapabilityLongCompositesINTEL: return "LongCompositesINTEL"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index 4e626c9..fb5d724 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -205,6 +205,7 @@ enum class ExecutionMode : unsigned { + SchedulerTargetFmaxMhzINTEL = 5903, + MaximallyReconvergesKHR = 6023, + FPFastMathDefault = 6028, ++ OpacityMicromapIdKHR = 6031, + StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, + NamedBarrierCountINTEL = 6417, +@@ -1270,6 +1271,7 @@ enum class Capability : unsigned { + DemoteToHelperInvocationEXT = 5379, + DisplacementMicromapNV = 5380, + RayTracingOpacityMicromapEXT = 5381, ++ RayTracingOpacityMicromapKHR = 5381, + ShaderInvocationReorderNV = 5383, + ShaderInvocationReorderEXT = 5388, + BindlessTextureNV = 5390, +@@ -1364,6 +1366,7 @@ enum class Capability : unsigned { + GroupNonUniformRotateKHR = 6026, + FloatControls2 = 6029, + FMAKHR = 6030, ++ RayTracingOpacityMicromapExecutionModeKHR = 6032, + AtomicFloat32AddEXT = 6033, + AtomicFloat64AddEXT = 6034, + LongCompositesINTEL = 6089, +@@ -1424,6 +1427,7 @@ enum class RayFlagsShift : unsigned { + SkipTrianglesKHR = 8, + SkipAABBsKHR = 9, + ForceOpacityMicromap2StateEXT = 10, ++ ForceOpacityMicromap2StateKHR = 10, + Max = 0x7fffffff, + }; + +@@ -1441,6 +1445,7 @@ enum class RayFlagsMask : unsigned { + SkipTrianglesKHR = 0x00000100, + SkipAABBsKHR = 0x00000200, + ForceOpacityMicromap2StateEXT = 0x00000400, ++ ForceOpacityMicromap2StateKHR = 0x00000400, + }; + + enum class RayQueryIntersection : unsigned { +@@ -3692,6 +3697,7 @@ inline const char* ExecutionModeToString(ExecutionMode value) { + case ExecutionMode::SchedulerTargetFmaxMhzINTEL: return "SchedulerTargetFmaxMhzINTEL"; + case ExecutionMode::MaximallyReconvergesKHR: return "MaximallyReconvergesKHR"; + case ExecutionMode::FPFastMathDefault: return "FPFastMathDefault"; ++ case ExecutionMode::OpacityMicromapIdKHR: return "OpacityMicromapIdKHR"; + case ExecutionMode::StreamingInterfaceINTEL: return "StreamingInterfaceINTEL"; + case ExecutionMode::RegisterMapInterfaceINTEL: return "RegisterMapInterfaceINTEL"; + case ExecutionMode::NamedBarrierCountINTEL: return "NamedBarrierCountINTEL"; +@@ -4501,6 +4507,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::GroupNonUniformRotateKHR: return "GroupNonUniformRotateKHR"; + case Capability::FloatControls2: return "FloatControls2"; + case Capability::FMAKHR: return "FMAKHR"; ++ case Capability::RayTracingOpacityMicromapExecutionModeKHR: return "RayTracingOpacityMicromapExecutionModeKHR"; + case Capability::AtomicFloat32AddEXT: return "AtomicFloat32AddEXT"; + case Capability::AtomicFloat64AddEXT: return "AtomicFloat64AddEXT"; + case Capability::LongCompositesINTEL: return "LongCompositesINTEL"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 135663c..af571b5 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -224,6 +224,7 @@ + "SchedulerTargetFmaxMhzINTEL": 5903, + "MaximallyReconvergesKHR": 6023, + "FPFastMathDefault": 6028, ++ "OpacityMicromapIdKHR": 6031, + "StreamingInterfaceINTEL": 6154, + "RegisterMapInterfaceINTEL": 6160, + "NamedBarrierCountINTEL": 6417, +@@ -1236,6 +1237,7 @@ + "DemoteToHelperInvocationEXT": 5379, + "DisplacementMicromapNV": 5380, + "RayTracingOpacityMicromapEXT": 5381, ++ "RayTracingOpacityMicromapKHR": 5381, + "ShaderInvocationReorderNV": 5383, + "ShaderInvocationReorderEXT": 5388, + "BindlessTextureNV": 5390, +@@ -1330,6 +1332,7 @@ + "GroupNonUniformRotateKHR": 6026, + "FloatControls2": 6029, + "FMAKHR": 6030, ++ "RayTracingOpacityMicromapExecutionModeKHR": 6032, + "AtomicFloat32AddEXT": 6033, + "AtomicFloat64AddEXT": 6034, + "LongCompositesINTEL": 6089, +@@ -1392,7 +1395,8 @@ + "SkipBuiltinPrimitivesNV": 8, + "SkipTrianglesKHR": 8, + "SkipAABBsKHR": 9, +- "ForceOpacityMicromap2StateEXT": 10 ++ "ForceOpacityMicromap2StateEXT": 10, ++ "ForceOpacityMicromap2StateKHR": 10 + } + }, + { +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index 8cbe093..f3da312 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -196,6 +196,7 @@ spv = { + SchedulerTargetFmaxMhzINTEL = 5903, + MaximallyReconvergesKHR = 6023, + FPFastMathDefault = 6028, ++ OpacityMicromapIdKHR = 6031, + StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, + NamedBarrierCountINTEL = 6417, +@@ -1261,6 +1262,7 @@ spv = { + DemoteToHelperInvocationEXT = 5379, + DisplacementMicromapNV = 5380, + RayTracingOpacityMicromapEXT = 5381, ++ RayTracingOpacityMicromapKHR = 5381, + ShaderInvocationReorderNV = 5383, + ShaderInvocationReorderEXT = 5388, + BindlessTextureNV = 5390, +@@ -1355,6 +1357,7 @@ spv = { + GroupNonUniformRotateKHR = 6026, + FloatControls2 = 6029, + FMAKHR = 6030, ++ RayTracingOpacityMicromapExecutionModeKHR = 6032, + AtomicFloat32AddEXT = 6033, + AtomicFloat64AddEXT = 6034, + LongCompositesINTEL = 6089, +@@ -1415,6 +1418,7 @@ spv = { + SkipTrianglesKHR = 8, + SkipAABBsKHR = 9, + ForceOpacityMicromap2StateEXT = 10, ++ ForceOpacityMicromap2StateKHR = 10, + Max = 0x7fffffff, + }, + +@@ -1432,6 +1436,7 @@ spv = { + SkipTrianglesKHR = 0x00000100, + SkipAABBsKHR = 0x00000200, + ForceOpacityMicromap2StateEXT = 0x00000400, ++ ForceOpacityMicromap2StateKHR = 0x00000400, + }, + + RayQueryIntersection = { +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index bb65ae9..88e5cbc 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -192,6 +192,7 @@ spv = { + 'SchedulerTargetFmaxMhzINTEL' : 5903, + 'MaximallyReconvergesKHR' : 6023, + 'FPFastMathDefault' : 6028, ++ 'OpacityMicromapIdKHR' : 6031, + 'StreamingInterfaceINTEL' : 6154, + 'RegisterMapInterfaceINTEL' : 6160, + 'NamedBarrierCountINTEL' : 6417, +@@ -1232,6 +1233,7 @@ spv = { + 'DemoteToHelperInvocationEXT' : 5379, + 'DisplacementMicromapNV' : 5380, + 'RayTracingOpacityMicromapEXT' : 5381, ++ 'RayTracingOpacityMicromapKHR' : 5381, + 'ShaderInvocationReorderNV' : 5383, + 'ShaderInvocationReorderEXT' : 5388, + 'BindlessTextureNV' : 5390, +@@ -1326,6 +1328,7 @@ spv = { + 'GroupNonUniformRotateKHR' : 6026, + 'FloatControls2' : 6029, + 'FMAKHR' : 6030, ++ 'RayTracingOpacityMicromapExecutionModeKHR' : 6032, + 'AtomicFloat32AddEXT' : 6033, + 'AtomicFloat64AddEXT' : 6034, + 'LongCompositesINTEL' : 6089, +@@ -1385,6 +1388,7 @@ spv = { + 'SkipTrianglesKHR' : 8, + 'SkipAABBsKHR' : 9, + 'ForceOpacityMicromap2StateEXT' : 10, ++ 'ForceOpacityMicromap2StateKHR' : 10, + }, + + 'RayFlagsMask' : { +@@ -1401,6 +1405,7 @@ spv = { + 'SkipTrianglesKHR' : 0x00000100, + 'SkipAABBsKHR' : 0x00000200, + 'ForceOpacityMicromap2StateEXT' : 0x00000400, ++ 'ForceOpacityMicromap2StateKHR' : 0x00000400, + }, + + 'RayQueryIntersection' : { +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 8d31fee..aab392c 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -208,6 +208,7 @@ enum ExecutionMode : uint + SchedulerTargetFmaxMhzINTEL = 5903, + MaximallyReconvergesKHR = 6023, + FPFastMathDefault = 6028, ++ OpacityMicromapIdKHR = 6031, + StreamingInterfaceINTEL = 6154, + RegisterMapInterfaceINTEL = 6160, + NamedBarrierCountINTEL = 6417, +@@ -1306,6 +1307,7 @@ enum Capability : uint + DemoteToHelperInvocationEXT = 5379, + DisplacementMicromapNV = 5380, + RayTracingOpacityMicromapEXT = 5381, ++ RayTracingOpacityMicromapKHR = 5381, + ShaderInvocationReorderNV = 5383, + ShaderInvocationReorderEXT = 5388, + BindlessTextureNV = 5390, +@@ -1400,6 +1402,7 @@ enum Capability : uint + GroupNonUniformRotateKHR = 6026, + FloatControls2 = 6029, + FMAKHR = 6030, ++ RayTracingOpacityMicromapExecutionModeKHR = 6032, + AtomicFloat32AddEXT = 6033, + AtomicFloat64AddEXT = 6034, + LongCompositesINTEL = 6089, +@@ -1461,6 +1464,7 @@ enum RayFlagsShift : uint + SkipTrianglesKHR = 8, + SkipAABBsKHR = 9, + ForceOpacityMicromap2StateEXT = 10, ++ ForceOpacityMicromap2StateKHR = 10, + Max = 0x7fffffff, + } + +@@ -1479,6 +1483,7 @@ enum RayFlagsMask : uint + SkipTrianglesKHR = 0x00000100, + SkipAABBsKHR = 0x00000200, + ForceOpacityMicromap2StateEXT = 0x00000400, ++ ForceOpacityMicromap2StateKHR = 0x00000400, + } + + enum RayQueryIntersection : uint +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0012-Add-NonSemanticGraphDebugInfo-instruction-set-591.patch b/internal/rosa/package/spirv/0012-Add-NonSemanticGraphDebugInfo-instruction-set-591.patch new file mode 100644 index 00000000..39c727b0 --- /dev/null +++ b/internal/rosa/package/spirv/0012-Add-NonSemanticGraphDebugInfo-instruction-set-591.patch @@ -0,0 +1,128 @@ +From 3541d11cabd489bfa898ce2da631efab9870979b Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?K=C3=A9vin=20Petit?= <kevin.petit@arm.com> +Date: Wed, 13 May 2026 16:59:08 +0100 +Subject: [PATCH 12/26] Add NonSemanticGraphDebugInfo instruction set (#591) + +Change-Id: Ibd080a73abc630fbd2b3068f9c22ab8c0e01c806 + +Signed-off-by: Kevin Petit <kevin.petit@arm.com> +--- + BUILD.bazel | 6 ++++ + .../unified1/NonSemanticGraphDebugInfo.h | 28 +++++++++++++++ + ...t.nonsemantic.graph.debuginfo.grammar.json | 35 +++++++++++++++++++ + tools/buildHeaders/bin/makeExtinstHeaders.py | 1 + + 4 files changed, 70 insertions(+) + create mode 100644 include/spirv/unified1/NonSemanticGraphDebugInfo.h + create mode 100644 include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json + +diff --git a/BUILD.bazel b/BUILD.bazel +index badf2c1..61ef7e8 100644 +--- a/BUILD.bazel ++++ b/BUILD.bazel +@@ -138,6 +138,11 @@ filegroup( + srcs = ["include/spirv/unified1/extinst.arm.motion-engine.100.grammar.json"], + ) + ++filegroup( ++ name = "spirv_ext_inst_non_semantic_graph_debuginfo_grammar_unified1", ++ srcs = ["include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json"], ++) ++ + cc_library( + name = "spirv_common_headers", + hdrs = [ +@@ -152,6 +157,7 @@ cc_library( + "include/spirv/unified1/NonSemanticClspvReflection.h", + "include/spirv/unified1/NonSemanticDebugBreak.h", + "include/spirv/unified1/NonSemanticDebugPrintf.h", ++ "include/spirv/unified1/NonSemanticGraphDebugInfo.h", + "include/spirv/unified1/NonSemanticShaderDebugInfo.h", + "include/spirv/unified1/NonSemanticShaderDebugInfo100.h", + "include/spirv/unified1/NonSemanticVkspReflection.h", +diff --git a/include/spirv/unified1/NonSemanticGraphDebugInfo.h b/include/spirv/unified1/NonSemanticGraphDebugInfo.h +new file mode 100644 +index 0000000..3046842 +--- /dev/null ++++ b/include/spirv/unified1/NonSemanticGraphDebugInfo.h +@@ -0,0 +1,28 @@ ++// SPDX-FileCopyrightText: 2022-2026 Arm Ltd. ++// SPDX-License-Identifier: MIT ++ ++#ifndef SPIRV_UNIFIED1_NonSemanticGraphDebugInfo_H_ ++#define SPIRV_UNIFIED1_NonSemanticGraphDebugInfo_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++enum { ++ NonSemanticGraphDebugInfoRevision = 1, ++ NonSemanticGraphDebugInfoRevision_BitWidthPadding = 0x7fffffff ++}; ++ ++enum NonSemanticGraphDebugInfoInstructions { ++ NonSemanticGraphDebugInfoDebugGraph = 1, ++ NonSemanticGraphDebugInfoDebugOperation = 2, ++ NonSemanticGraphDebugInfoDebugTensor = 3, ++ NonSemanticGraphDebugInfoInstructionsMax = 0x7fffffff ++}; ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // SPIRV_UNIFIED1_NonSemanticGraphDebugInfo_H_ +diff --git a/include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json b/include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json +new file mode 100644 +index 0000000..b740775 +--- /dev/null ++++ b/include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json +@@ -0,0 +1,35 @@ ++{ ++ "copyright": [ ++ "SPDX-FileCopyrightText: 2022-2026 Arm Ltd.", ++ "SPDX-License-Identifier: MIT" ++ ], ++ "revision" : 1, ++ "instructions" : [ ++ { ++ "opname" : "DebugGraph", ++ "opcode" : 1, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "Graph" }, ++ { "kind" : "IdRef", "name" : "Name" } ++ ] ++ }, ++ { ++ "opname" : "DebugOperation", ++ "opcode" : 2, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "DebugGraph" }, ++ { "kind" : "IdRef", "name" : "Name" }, ++ { "kind" : "IdRef", "name" : "Instructions", "quantifier" : "*" } ++ ] ++ }, ++ { ++ "opname" : "DebugTensor", ++ "opcode" : 3, ++ "operands" : [ ++ { "kind" : "IdRef", "name" : "Tensor" }, ++ { "kind" : "IdRef", "name" : "Name" }, ++ { "kind" : "IdRef", "name" : "Index", "quantifier" : "?" } ++ ] ++ } ++ ] ++} +diff --git a/tools/buildHeaders/bin/makeExtinstHeaders.py b/tools/buildHeaders/bin/makeExtinstHeaders.py +index e5fd640..1c9fbfd 100755 +--- a/tools/buildHeaders/bin/makeExtinstHeaders.py ++++ b/tools/buildHeaders/bin/makeExtinstHeaders.py +@@ -31,3 +31,4 @@ mk_extinst('NonSemanticDebugBreak', 'extinst.nonsemantic.debugbreak.grammar.json + mk_extinst('NonSemanticVkspReflection', 'extinst.nonsemantic.vkspreflection.grammar.json') + mk_extinst('TOSA', 'extinst.tosa.001000.1.grammar.json', 'TOSA.001000.1') + mk_extinst('ArmMotionEngine', 'extinst.arm.motion-engine.100.grammar.json', 'ArmMotionEngine.100') ++mk_extinst('NonSemanticGraphDebugInfo', 'extinst.nonsemantic.graph.debuginfo.grammar.json') +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0013-Revert-Add-SPV_MESA_fragment_coverage_mask-enumerant.patch b/internal/rosa/package/spirv/0013-Revert-Add-SPV_MESA_fragment_coverage_mask-enumerant.patch new file mode 100644 index 00000000..52a11ed9 --- /dev/null +++ b/internal/rosa/package/spirv/0013-Revert-Add-SPV_MESA_fragment_coverage_mask-enumerant.patch @@ -0,0 +1,282 @@ +From 82dfca37143878c848d8df1f9e4d746f65e6827e Mon Sep 17 00:00:00 2001 +From: Faith Ekstrand <faith.ekstrand@collabora.com> +Date: Wed, 13 May 2026 12:00:42 -0400 +Subject: [PATCH 13/26] Revert "Add SPV_MESA_fragment_coverage_mask enumerants + (#580)" (#598) + +This reverts commit 157de8e260e9362225c0ce9a6675d034968abe15. +--- + include/spirv/unified1/spirv.bf | 2 -- + include/spirv/unified1/spirv.core.grammar.json | 13 ------------- + include/spirv/unified1/spirv.cs | 2 -- + include/spirv/unified1/spirv.h | 4 ---- + include/spirv/unified1/spirv.hpp | 4 ---- + include/spirv/unified1/spirv.hpp11 | 4 ---- + include/spirv/unified1/spirv.json | 2 -- + include/spirv/unified1/spirv.lua | 2 -- + include/spirv/unified1/spirv.py | 2 -- + include/spirv/unified1/spv.d | 2 -- + 10 files changed, 37 deletions(-) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index a512a3e..119ea89 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -759,7 +759,6 @@ namespace Spv + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, +- FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1172,7 +1171,6 @@ namespace Spv + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, +- FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 32a350a..0f1b083 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -16185,12 +16185,6 @@ + "capabilities" : [ "Shader" ], + "version": "1.0" + }, +- { +- "enumerant" : "FragmentCoverageMaskMESA", +- "value" : 4096, +- "capabilities" : [ "FragmentCoverageMESA" ], +- "version" : "None" +- }, + { + "enumerant" : "CoreIDARM", + "value" : 4160, +@@ -17330,13 +17324,6 @@ + "value" : 71, + "version" : "1.6" + }, +- { +- "enumerant" : "FragmentCoverageMESA", +- "value" : 4097, +- "capabilities" : [ "Shader" ], +- "extensions" : [ "SPV_MESA_fragment_coverage_mask" ], +- "version" : "None" +- }, + { + "enumerant" : "CoreBuiltinsARM", + "value" : 4165, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 4d33ffa..7f66ede 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -758,7 +758,6 @@ namespace Spv + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, +- FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1171,7 +1170,6 @@ namespace Spv + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, +- FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index d9dedc0..99b983c 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -745,7 +745,6 @@ typedef enum SpvBuiltIn_ { + SpvBuiltInSubgroupLocalInvocationId = 41, + SpvBuiltInVertexIndex = 42, + SpvBuiltInInstanceIndex = 43, +- SpvBuiltInFragmentCoverageMaskMESA = 4096, + SpvBuiltInCoreIDARM = 4160, + SpvBuiltInCoreCountARM = 4161, + SpvBuiltInCoreMaxIDARM = 4162, +@@ -1142,7 +1141,6 @@ typedef enum SpvCapability_ { + SpvCapabilityShaderLayer = 69, + SpvCapabilityShaderViewportIndex = 70, + SpvCapabilityUniformDecoration = 71, +- SpvCapabilityFragmentCoverageMESA = 4097, + SpvCapabilityCoreBuiltinsARM = 4165, + SpvCapabilityTileImageColorReadAccessEXT = 4166, + SpvCapabilityTileImageDepthReadAccessEXT = 4167, +@@ -4129,7 +4127,6 @@ inline const char* SpvBuiltInToString(SpvBuiltIn value) { + case SpvBuiltInSubgroupLocalInvocationId: return "SubgroupLocalInvocationId"; + case SpvBuiltInVertexIndex: return "VertexIndex"; + case SpvBuiltInInstanceIndex: return "InstanceIndex"; +- case SpvBuiltInFragmentCoverageMaskMESA: return "FragmentCoverageMaskMESA"; + case SpvBuiltInCoreIDARM: return "CoreIDARM"; + case SpvBuiltInCoreCountARM: return "CoreCountARM"; + case SpvBuiltInCoreMaxIDARM: return "CoreMaxIDARM"; +@@ -4328,7 +4325,6 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityShaderLayer: return "ShaderLayer"; + case SpvCapabilityShaderViewportIndex: return "ShaderViewportIndex"; + case SpvCapabilityUniformDecoration: return "UniformDecoration"; +- case SpvCapabilityFragmentCoverageMESA: return "FragmentCoverageMESA"; + case SpvCapabilityCoreBuiltinsARM: return "CoreBuiltinsARM"; + case SpvCapabilityTileImageColorReadAccessEXT: return "TileImageColorReadAccessEXT"; + case SpvCapabilityTileImageDepthReadAccessEXT: return "TileImageDepthReadAccessEXT"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index d0a1606..966be25 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -741,7 +741,6 @@ enum BuiltIn { + BuiltInSubgroupLocalInvocationId = 41, + BuiltInVertexIndex = 42, + BuiltInInstanceIndex = 43, +- BuiltInFragmentCoverageMaskMESA = 4096, + BuiltInCoreIDARM = 4160, + BuiltInCoreCountARM = 4161, + BuiltInCoreMaxIDARM = 4162, +@@ -1138,7 +1137,6 @@ enum Capability { + CapabilityShaderLayer = 69, + CapabilityShaderViewportIndex = 70, + CapabilityUniformDecoration = 71, +- CapabilityFragmentCoverageMESA = 4097, + CapabilityCoreBuiltinsARM = 4165, + CapabilityTileImageColorReadAccessEXT = 4166, + CapabilityTileImageDepthReadAccessEXT = 4167, +@@ -4125,7 +4123,6 @@ inline const char* BuiltInToString(BuiltIn value) { + case BuiltInSubgroupLocalInvocationId: return "SubgroupLocalInvocationId"; + case BuiltInVertexIndex: return "VertexIndex"; + case BuiltInInstanceIndex: return "InstanceIndex"; +- case BuiltInFragmentCoverageMaskMESA: return "FragmentCoverageMaskMESA"; + case BuiltInCoreIDARM: return "CoreIDARM"; + case BuiltInCoreCountARM: return "CoreCountARM"; + case BuiltInCoreMaxIDARM: return "CoreMaxIDARM"; +@@ -4324,7 +4321,6 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityShaderLayer: return "ShaderLayer"; + case CapabilityShaderViewportIndex: return "ShaderViewportIndex"; + case CapabilityUniformDecoration: return "UniformDecoration"; +- case CapabilityFragmentCoverageMESA: return "FragmentCoverageMESA"; + case CapabilityCoreBuiltinsARM: return "CoreBuiltinsARM"; + case CapabilityTileImageColorReadAccessEXT: return "TileImageColorReadAccessEXT"; + case CapabilityTileImageDepthReadAccessEXT: return "TileImageDepthReadAccessEXT"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index fb5d724..bdc4ac0 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -741,7 +741,6 @@ enum class BuiltIn : unsigned { + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, +- FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1138,7 +1137,6 @@ enum class Capability : unsigned { + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, +- FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +@@ -4125,7 +4123,6 @@ inline const char* BuiltInToString(BuiltIn value) { + case BuiltIn::SubgroupLocalInvocationId: return "SubgroupLocalInvocationId"; + case BuiltIn::VertexIndex: return "VertexIndex"; + case BuiltIn::InstanceIndex: return "InstanceIndex"; +- case BuiltIn::FragmentCoverageMaskMESA: return "FragmentCoverageMaskMESA"; + case BuiltIn::CoreIDARM: return "CoreIDARM"; + case BuiltIn::CoreCountARM: return "CoreCountARM"; + case BuiltIn::CoreMaxIDARM: return "CoreMaxIDARM"; +@@ -4324,7 +4321,6 @@ inline const char* CapabilityToString(Capability value) { + case Capability::ShaderLayer: return "ShaderLayer"; + case Capability::ShaderViewportIndex: return "ShaderViewportIndex"; + case Capability::UniformDecoration: return "UniformDecoration"; +- case Capability::FragmentCoverageMESA: return "FragmentCoverageMESA"; + case Capability::CoreBuiltinsARM: return "CoreBuiltinsARM"; + case Capability::TileImageColorReadAccessEXT: return "TileImageColorReadAccessEXT"; + case Capability::TileImageDepthReadAccessEXT: return "TileImageDepthReadAccessEXT"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index af571b5..eb646f6 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -767,7 +767,6 @@ + "SubgroupLocalInvocationId": 41, + "VertexIndex": 42, + "InstanceIndex": 43, +- "FragmentCoverageMaskMESA": 4096, + "CoreIDARM": 4160, + "CoreCountARM": 4161, + "CoreMaxIDARM": 4162, +@@ -1104,7 +1103,6 @@ + "ShaderLayer": 69, + "ShaderViewportIndex": 70, + "UniformDecoration": 71, +- "FragmentCoverageMESA": 4097, + "CoreBuiltinsARM": 4165, + "TileImageColorReadAccessEXT": 4166, + "TileImageDepthReadAccessEXT": 4167, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index f3da312..e425dd5 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -732,7 +732,6 @@ spv = { + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, +- FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1129,7 +1128,6 @@ spv = { + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, +- FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index 88e5cbc..a35941b 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -713,7 +713,6 @@ spv = { + 'SubgroupLocalInvocationId' : 41, + 'VertexIndex' : 42, + 'InstanceIndex' : 43, +- 'FragmentCoverageMaskMESA' : 4096, + 'CoreIDARM' : 4160, + 'CoreCountARM' : 4161, + 'CoreMaxIDARM' : 4162, +@@ -1100,7 +1099,6 @@ spv = { + 'ShaderLayer' : 69, + 'ShaderViewportIndex' : 70, + 'UniformDecoration' : 71, +- 'FragmentCoverageMESA' : 4097, + 'CoreBuiltinsARM' : 4165, + 'TileImageColorReadAccessEXT' : 4166, + 'TileImageDepthReadAccessEXT' : 4167, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index aab392c..8fa24b9 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -761,7 +761,6 @@ enum BuiltIn : uint + SubgroupLocalInvocationId = 41, + VertexIndex = 42, + InstanceIndex = 43, +- FragmentCoverageMaskMESA = 4096, + CoreIDARM = 4160, + CoreCountARM = 4161, + CoreMaxIDARM = 4162, +@@ -1174,7 +1173,6 @@ enum Capability : uint + ShaderLayer = 69, + ShaderViewportIndex = 70, + UniformDecoration = 71, +- FragmentCoverageMESA = 4097, + CoreBuiltinsARM = 4165, + TileImageColorReadAccessEXT = 4166, + TileImageDepthReadAccessEXT = 4167, +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0014-SPV_EXT_split_barrier-600.patch b/internal/rosa/package/spirv/0014-SPV_EXT_split_barrier-600.patch new file mode 100644 index 00000000..b4d97613 --- /dev/null +++ b/internal/rosa/package/spirv/0014-SPV_EXT_split_barrier-600.patch @@ -0,0 +1,366 @@ +From fe44b2002bf7871e2e92fc001bc9f6e09f92194f Mon Sep 17 00:00:00 2001 +From: Ralph Potter <r.potter@samsung.com> +Date: Thu, 14 May 2026 14:30:23 +0100 +Subject: [PATCH 14/26] SPV_EXT_split_barrier (#600) + +* SPV_EXT_split_barrier + +* Remove spurious capability +--- + include/spirv/unified1/spirv.bf | 3 +++ + include/spirv/unified1/spirv.core.grammar.json | 15 +++++++++------ + include/spirv/unified1/spirv.cs | 3 +++ + include/spirv/unified1/spirv.h | 13 ++++++++----- + include/spirv/unified1/spirv.hpp | 13 ++++++++----- + include/spirv/unified1/spirv.hpp11 | 13 ++++++++----- + include/spirv/unified1/spirv.json | 3 +++ + include/spirv/unified1/spirv.lua | 3 +++ + include/spirv/unified1/spirv.py | 3 +++ + include/spirv/unified1/spv.d | 3 +++ + 10 files changed, 51 insertions(+), 21 deletions(-) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 119ea89..0ecf295 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -1407,6 +1407,7 @@ namespace Spv + AtomicFloat16AddEXT = 6095, + DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, ++ SplitBarrierEXT = 6141, + SplitBarrierINTEL = 6141, + ArithmeticFenceEXT = 6144, + FPGAClusterAttributesV2ALTERA = 6150, +@@ -2674,7 +2675,9 @@ namespace Spv + OpCompositeConstructContinuedINTEL = 6096, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, ++ OpControlBarrierArriveEXT = 6142, + OpControlBarrierArriveINTEL = 6142, ++ OpControlBarrierWaitEXT = 6143, + OpControlBarrierWaitINTEL = 6143, + OpArithmeticFenceEXT = 6145, + OpTaskSequenceCreateALTERA = 6163, +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 0f1b083..b2b665b 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -11253,27 +11253,29 @@ + "version" : "None" + }, + { +- "opname" : "OpControlBarrierArriveINTEL", ++ "opname" : "OpControlBarrierArriveEXT", + "class" : "Barrier", ++ "aliases" : [ "OpControlBarrierArriveINTEL" ], + "opcode" : 6142, + "operands" : [ + { "kind" : "IdScope", "name" : "Execution" }, + { "kind" : "IdScope", "name" : "Memory" }, + { "kind" : "IdMemorySemantics", "name" : "Semantics" } + ], +- "capabilities" : [ "SplitBarrierINTEL" ], ++ "capabilities" : [ "SplitBarrierEXT" ], + "version" : "None" + }, + { +- "opname" : "OpControlBarrierWaitINTEL", ++ "opname" : "OpControlBarrierWaitEXT", + "class" : "Barrier", ++ "aliases" : [ "OpControlBarrierWaitINTEL" ], + "opcode" : 6143, + "operands" : [ + { "kind" : "IdScope", "name" : "Execution" }, + { "kind" : "IdScope", "name" : "Memory" }, + { "kind" : "IdMemorySemantics", "name" : "Semantics" } + ], +- "capabilities" : [ "SplitBarrierINTEL" ], ++ "capabilities" : [ "SplitBarrierEXT" ], + "version" : "None" + }, + { +@@ -18591,9 +18593,10 @@ + "version" : "None" + }, + { +- "enumerant" : "SplitBarrierINTEL", ++ "enumerant" : "SplitBarrierEXT", ++ "aliases" : [ "SplitBarrierINTEL" ], + "value" : 6141, +- "extensions" : [ "SPV_INTEL_split_barrier" ], ++ "extensions" : [ "SPV_EXT_split_barrier", "SPV_INTEL_split_barrier" ], + "version" : "None" + }, + { +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 7f66ede..06845bb 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -1406,6 +1406,7 @@ namespace Spv + AtomicFloat16AddEXT = 6095, + DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, ++ SplitBarrierEXT = 6141, + SplitBarrierINTEL = 6141, + ArithmeticFenceEXT = 6144, + FPGAClusterAttributesV2ALTERA = 6150, +@@ -2673,7 +2674,9 @@ namespace Spv + OpCompositeConstructContinuedINTEL = 6096, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, ++ OpControlBarrierArriveEXT = 6142, + OpControlBarrierArriveINTEL = 6142, ++ OpControlBarrierWaitEXT = 6143, + OpControlBarrierWaitINTEL = 6143, + OpArithmeticFenceEXT = 6145, + OpTaskSequenceCreateALTERA = 6163, +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 99b983c..964f5aa 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -1377,6 +1377,7 @@ typedef enum SpvCapability_ { + SpvCapabilityAtomicFloat16AddEXT = 6095, + SpvCapabilityDebugInfoModuleINTEL = 6114, + SpvCapabilityBFloat16ConversionINTEL = 6115, ++ SpvCapabilitySplitBarrierEXT = 6141, + SpvCapabilitySplitBarrierINTEL = 6141, + SpvCapabilityArithmeticFenceEXT = 6144, + SpvCapabilityFPGAClusterAttributesV2ALTERA = 6150, +@@ -2608,7 +2609,9 @@ typedef enum SpvOp_ { + SpvOpCompositeConstructContinuedINTEL = 6096, + SpvOpConvertFToBF16INTEL = 6116, + SpvOpConvertBF16ToFINTEL = 6117, ++ SpvOpControlBarrierArriveEXT = 6142, + SpvOpControlBarrierArriveINTEL = 6142, ++ SpvOpControlBarrierWaitEXT = 6143, + SpvOpControlBarrierWaitINTEL = 6143, + SpvOpArithmeticFenceEXT = 6145, + SpvOpTaskSequenceCreateALTERA = 6163, +@@ -3497,8 +3500,8 @@ inline void SpvHasResultAndType(SpvOp opcode, bool *hasResult, bool *hasResultTy + case SpvOpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case SpvOpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case SpvOpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; +- case SpvOpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; +- case SpvOpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; ++ case SpvOpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break; ++ case SpvOpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break; + case SpvOpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break; + case SpvOpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break; + case SpvOpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break; +@@ -4515,7 +4518,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT"; + case SpvCapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL"; + case SpvCapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL"; +- case SpvCapabilitySplitBarrierINTEL: return "SplitBarrierINTEL"; ++ case SpvCapabilitySplitBarrierEXT: return "SplitBarrierEXT"; + case SpvCapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT"; + case SpvCapabilityFPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA"; + case SpvCapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL"; +@@ -5570,8 +5573,8 @@ inline const char* SpvOpToString(SpvOp value) { + case SpvOpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL"; + case SpvOpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL"; + case SpvOpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL"; +- case SpvOpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL"; +- case SpvOpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL"; ++ case SpvOpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT"; ++ case SpvOpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT"; + case SpvOpArithmeticFenceEXT: return "OpArithmeticFenceEXT"; + case SpvOpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA"; + case SpvOpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 966be25..655a79c 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -1373,6 +1373,7 @@ enum Capability { + CapabilityAtomicFloat16AddEXT = 6095, + CapabilityDebugInfoModuleINTEL = 6114, + CapabilityBFloat16ConversionINTEL = 6115, ++ CapabilitySplitBarrierEXT = 6141, + CapabilitySplitBarrierINTEL = 6141, + CapabilityArithmeticFenceEXT = 6144, + CapabilityFPGAClusterAttributesV2ALTERA = 6150, +@@ -2604,7 +2605,9 @@ enum Op { + OpCompositeConstructContinuedINTEL = 6096, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, ++ OpControlBarrierArriveEXT = 6142, + OpControlBarrierArriveINTEL = 6142, ++ OpControlBarrierWaitEXT = 6143, + OpControlBarrierWaitINTEL = 6143, + OpArithmeticFenceEXT = 6145, + OpTaskSequenceCreateALTERA = 6163, +@@ -3493,8 +3496,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; +- case OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; +- case OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; ++ case OpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break; ++ case OpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break; + case OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break; + case OpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break; + case OpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break; +@@ -4511,7 +4514,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityAtomicFloat16AddEXT: return "AtomicFloat16AddEXT"; + case CapabilityDebugInfoModuleINTEL: return "DebugInfoModuleINTEL"; + case CapabilityBFloat16ConversionINTEL: return "BFloat16ConversionINTEL"; +- case CapabilitySplitBarrierINTEL: return "SplitBarrierINTEL"; ++ case CapabilitySplitBarrierEXT: return "SplitBarrierEXT"; + case CapabilityArithmeticFenceEXT: return "ArithmeticFenceEXT"; + case CapabilityFPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA"; + case CapabilityFPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL"; +@@ -5566,8 +5569,8 @@ inline const char* OpToString(Op value) { + case OpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL"; + case OpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL"; + case OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL"; +- case OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL"; +- case OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL"; ++ case OpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT"; ++ case OpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT"; + case OpArithmeticFenceEXT: return "OpArithmeticFenceEXT"; + case OpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA"; + case OpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index bdc4ac0..270b33f 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -1373,6 +1373,7 @@ enum class Capability : unsigned { + AtomicFloat16AddEXT = 6095, + DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, ++ SplitBarrierEXT = 6141, + SplitBarrierINTEL = 6141, + ArithmeticFenceEXT = 6144, + FPGAClusterAttributesV2ALTERA = 6150, +@@ -2604,7 +2605,9 @@ enum class Op : unsigned { + OpCompositeConstructContinuedINTEL = 6096, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, ++ OpControlBarrierArriveEXT = 6142, + OpControlBarrierArriveINTEL = 6142, ++ OpControlBarrierWaitEXT = 6143, + OpControlBarrierWaitINTEL = 6143, + OpArithmeticFenceEXT = 6145, + OpTaskSequenceCreateALTERA = 6163, +@@ -3493,8 +3496,8 @@ inline void HasResultAndType(Op opcode, bool *hasResult, bool *hasResultType) { + case Op::OpCompositeConstructContinuedINTEL: *hasResult = false; *hasResultType = false; break; + case Op::OpConvertFToBF16INTEL: *hasResult = true; *hasResultType = true; break; + case Op::OpConvertBF16ToFINTEL: *hasResult = true; *hasResultType = true; break; +- case Op::OpControlBarrierArriveINTEL: *hasResult = false; *hasResultType = false; break; +- case Op::OpControlBarrierWaitINTEL: *hasResult = false; *hasResultType = false; break; ++ case Op::OpControlBarrierArriveEXT: *hasResult = false; *hasResultType = false; break; ++ case Op::OpControlBarrierWaitEXT: *hasResult = false; *hasResultType = false; break; + case Op::OpArithmeticFenceEXT: *hasResult = true; *hasResultType = true; break; + case Op::OpTaskSequenceCreateALTERA: *hasResult = true; *hasResultType = true; break; + case Op::OpTaskSequenceAsyncALTERA: *hasResult = false; *hasResultType = false; break; +@@ -4511,7 +4514,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::AtomicFloat16AddEXT: return "AtomicFloat16AddEXT"; + case Capability::DebugInfoModuleINTEL: return "DebugInfoModuleINTEL"; + case Capability::BFloat16ConversionINTEL: return "BFloat16ConversionINTEL"; +- case Capability::SplitBarrierINTEL: return "SplitBarrierINTEL"; ++ case Capability::SplitBarrierEXT: return "SplitBarrierEXT"; + case Capability::ArithmeticFenceEXT: return "ArithmeticFenceEXT"; + case Capability::FPGAClusterAttributesV2ALTERA: return "FPGAClusterAttributesV2ALTERA"; + case Capability::FPGAKernelAttributesv2INTEL: return "FPGAKernelAttributesv2INTEL"; +@@ -5566,8 +5569,8 @@ inline const char* OpToString(Op value) { + case Op::OpCompositeConstructContinuedINTEL: return "OpCompositeConstructContinuedINTEL"; + case Op::OpConvertFToBF16INTEL: return "OpConvertFToBF16INTEL"; + case Op::OpConvertBF16ToFINTEL: return "OpConvertBF16ToFINTEL"; +- case Op::OpControlBarrierArriveINTEL: return "OpControlBarrierArriveINTEL"; +- case Op::OpControlBarrierWaitINTEL: return "OpControlBarrierWaitINTEL"; ++ case Op::OpControlBarrierArriveEXT: return "OpControlBarrierArriveEXT"; ++ case Op::OpControlBarrierWaitEXT: return "OpControlBarrierWaitEXT"; + case Op::OpArithmeticFenceEXT: return "OpArithmeticFenceEXT"; + case Op::OpTaskSequenceCreateALTERA: return "OpTaskSequenceCreateALTERA"; + case Op::OpTaskSequenceAsyncALTERA: return "OpTaskSequenceAsyncALTERA"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index eb646f6..5a21f07 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -1339,6 +1339,7 @@ + "AtomicFloat16AddEXT": 6095, + "DebugInfoModuleINTEL": 6114, + "BFloat16ConversionINTEL": 6115, ++ "SplitBarrierEXT": 6141, + "SplitBarrierINTEL": 6141, + "ArithmeticFenceEXT": 6144, + "FPGAClusterAttributesV2ALTERA": 6150, +@@ -2574,7 +2575,9 @@ + "OpCompositeConstructContinuedINTEL": 6096, + "OpConvertFToBF16INTEL": 6116, + "OpConvertBF16ToFINTEL": 6117, ++ "OpControlBarrierArriveEXT": 6142, + "OpControlBarrierArriveINTEL": 6142, ++ "OpControlBarrierWaitEXT": 6143, + "OpControlBarrierWaitINTEL": 6143, + "OpArithmeticFenceEXT": 6145, + "OpTaskSequenceCreateALTERA": 6163, +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index e425dd5..64b0a1f 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -1364,6 +1364,7 @@ spv = { + AtomicFloat16AddEXT = 6095, + DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, ++ SplitBarrierEXT = 6141, + SplitBarrierINTEL = 6141, + ArithmeticFenceEXT = 6144, + FPGAClusterAttributesV2ALTERA = 6150, +@@ -2595,7 +2596,9 @@ spv = { + OpCompositeConstructContinuedINTEL = 6096, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, ++ OpControlBarrierArriveEXT = 6142, + OpControlBarrierArriveINTEL = 6142, ++ OpControlBarrierWaitEXT = 6143, + OpControlBarrierWaitINTEL = 6143, + OpArithmeticFenceEXT = 6145, + OpTaskSequenceCreateALTERA = 6163, +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index a35941b..5f3bae6 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -1335,6 +1335,7 @@ spv = { + 'AtomicFloat16AddEXT' : 6095, + 'DebugInfoModuleINTEL' : 6114, + 'BFloat16ConversionINTEL' : 6115, ++ 'SplitBarrierEXT' : 6141, + 'SplitBarrierINTEL' : 6141, + 'ArithmeticFenceEXT' : 6144, + 'FPGAClusterAttributesV2ALTERA' : 6150, +@@ -2538,7 +2539,9 @@ spv = { + 'OpCompositeConstructContinuedINTEL' : 6096, + 'OpConvertFToBF16INTEL' : 6116, + 'OpConvertBF16ToFINTEL' : 6117, ++ 'OpControlBarrierArriveEXT' : 6142, + 'OpControlBarrierArriveINTEL' : 6142, ++ 'OpControlBarrierWaitEXT' : 6143, + 'OpControlBarrierWaitINTEL' : 6143, + 'OpArithmeticFenceEXT' : 6145, + 'OpTaskSequenceCreateALTERA' : 6163, +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 8fa24b9..4e4e3dc 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -1409,6 +1409,7 @@ enum Capability : uint + AtomicFloat16AddEXT = 6095, + DebugInfoModuleINTEL = 6114, + BFloat16ConversionINTEL = 6115, ++ SplitBarrierEXT = 6141, + SplitBarrierINTEL = 6141, + ArithmeticFenceEXT = 6144, + FPGAClusterAttributesV2ALTERA = 6150, +@@ -2676,7 +2677,9 @@ enum Op : uint + OpCompositeConstructContinuedINTEL = 6096, + OpConvertFToBF16INTEL = 6116, + OpConvertBF16ToFINTEL = 6117, ++ OpControlBarrierArriveEXT = 6142, + OpControlBarrierArriveINTEL = 6142, ++ OpControlBarrierWaitEXT = 6143, + OpControlBarrierWaitINTEL = 6143, + OpArithmeticFenceEXT = 6145, + OpTaskSequenceCreateALTERA = 6163, +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0015-SPV_NV_cooperative_matrix_decode_vector-601.patch b/internal/rosa/package/spirv/0015-SPV_NV_cooperative_matrix_decode_vector-601.patch new file mode 100644 index 00000000..67575ed8 --- /dev/null +++ b/internal/rosa/package/spirv/0015-SPV_NV_cooperative_matrix_decode_vector-601.patch @@ -0,0 +1,324 @@ +From aaffbc59b41bf8faea671b0d1c6b34a584c45171 Mon Sep 17 00:00:00 2001 +From: Jeff Bolz <jbolz@nvidia.com> +Date: Fri, 15 May 2026 10:51:25 -0500 +Subject: [PATCH 15/26] SPV_NV_cooperative_matrix_decode_vector (#601) + +--- + include/spirv/unified1/spirv.bf | 3 +++ + include/spirv/unified1/spirv.core.grammar.json | 16 ++++++++++++++++ + include/spirv/unified1/spirv.cs | 3 +++ + include/spirv/unified1/spirv.h | 4 ++++ + include/spirv/unified1/spirv.hpp | 4 ++++ + include/spirv/unified1/spirv.hpp11 | 4 ++++ + include/spirv/unified1/spirv.json | 4 +++- + include/spirv/unified1/spirv.lua | 3 +++ + include/spirv/unified1/spirv.py | 3 +++ + include/spirv/unified1/spv.d | 3 +++ + 10 files changed, 46 insertions(+), 1 deletion(-) + +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 0ecf295..9497023 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -1325,6 +1325,7 @@ namespace Spv + CooperativeVectorTrainingNV = 5435, + RayTracingClusterAccelerationStructureNV = 5437, + TensorAddressingNV = 5439, ++ CooperativeMatrixDecodeVectorNV = 5447, + SubgroupShuffleINTEL = 5568, + SubgroupBufferBlockIOINTEL = 5569, + SubgroupImageBlockIOINTEL = 5570, +@@ -1633,6 +1634,7 @@ namespace Spv + { + TensorView = 0, + DecodeFunc = 1, ++ DecodeVectorFunc = 2, + Max = 0x7fffffff, + } + +@@ -1641,6 +1643,7 @@ namespace Spv + MaskNone = 0, + TensorView = 0x00000001, + DecodeFunc = 0x00000002, ++ DecodeVectorFunc = 0x00000004, + } + + [AllowDuplicates, CRepr] public enum TensorOperandsShift +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index b2b665b..4f96982 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -18200,6 +18200,13 @@ + "extensions" : [ "SPV_NV_tensor_addressing" ], + "version" : "None" + }, ++ { ++ "enumerant" : "CooperativeMatrixDecodeVectorNV", ++ "value" : 5447, ++ "capabilities" : [ "CooperativeMatrixBlockLoadsNV" ], ++ "extensions" : [ "SPV_NV_cooperative_matrix_decode_vector" ], ++ "version" : "None" ++ }, + { + "enumerant" : "SubgroupShuffleINTEL", + "value" : 5568, +@@ -19035,6 +19042,15 @@ + ], + "capabilities" : [ "CooperativeMatrixBlockLoadsNV" ], + "version" : "None" ++ }, ++ { ++ "enumerant" : "DecodeVectorFunc", ++ "value" : "0x0004", ++ "parameters" : [ ++ { "kind" : "IdRef" } ++ ], ++ "capabilities" : [ "CooperativeMatrixDecodeVectorNV" ], ++ "version" : "None" + } + ] + }, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 06845bb..7631bf2 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -1324,6 +1324,7 @@ namespace Spv + CooperativeVectorTrainingNV = 5435, + RayTracingClusterAccelerationStructureNV = 5437, + TensorAddressingNV = 5439, ++ CooperativeMatrixDecodeVectorNV = 5447, + SubgroupShuffleINTEL = 5568, + SubgroupBufferBlockIOINTEL = 5569, + SubgroupImageBlockIOINTEL = 5570, +@@ -1632,6 +1633,7 @@ namespace Spv + { + TensorView = 0, + DecodeFunc = 1, ++ DecodeVectorFunc = 2, + Max = 0x7fffffff, + } + +@@ -1640,6 +1642,7 @@ namespace Spv + MaskNone = 0, + TensorView = 0x00000001, + DecodeFunc = 0x00000002, ++ DecodeVectorFunc = 0x00000004, + } + + public enum TensorOperandsShift +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 964f5aa..5ab265f 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -1295,6 +1295,7 @@ typedef enum SpvCapability_ { + SpvCapabilityCooperativeVectorTrainingNV = 5435, + SpvCapabilityRayTracingClusterAccelerationStructureNV = 5437, + SpvCapabilityTensorAddressingNV = 5439, ++ SpvCapabilityCooperativeMatrixDecodeVectorNV = 5447, + SpvCapabilitySubgroupShuffleINTEL = 5568, + SpvCapabilitySubgroupBufferBlockIOINTEL = 5569, + SpvCapabilitySubgroupImageBlockIOINTEL = 5570, +@@ -1583,6 +1584,7 @@ typedef enum SpvTensorClampMode_ { + typedef enum SpvTensorAddressingOperandsShift_ { + SpvTensorAddressingOperandsTensorViewShift = 0, + SpvTensorAddressingOperandsDecodeFuncShift = 1, ++ SpvTensorAddressingOperandsDecodeVectorFuncShift = 2, + SpvTensorAddressingOperandsMax = 0x7fffffff, + } SpvTensorAddressingOperandsShift; + +@@ -1590,6 +1592,7 @@ typedef enum SpvTensorAddressingOperandsMask_ { + SpvTensorAddressingOperandsMaskNone = 0, + SpvTensorAddressingOperandsTensorViewMask = 0x00000001, + SpvTensorAddressingOperandsDecodeFuncMask = 0x00000002, ++ SpvTensorAddressingOperandsDecodeVectorFuncMask = 0x00000004, + } SpvTensorAddressingOperandsMask; + + typedef enum SpvTensorOperandsShift_ { +@@ -4457,6 +4460,7 @@ inline const char* SpvCapabilityToString(SpvCapability value) { + case SpvCapabilityCooperativeVectorTrainingNV: return "CooperativeVectorTrainingNV"; + case SpvCapabilityRayTracingClusterAccelerationStructureNV: return "RayTracingClusterAccelerationStructureNV"; + case SpvCapabilityTensorAddressingNV: return "TensorAddressingNV"; ++ case SpvCapabilityCooperativeMatrixDecodeVectorNV: return "CooperativeMatrixDecodeVectorNV"; + case SpvCapabilitySubgroupShuffleINTEL: return "SubgroupShuffleINTEL"; + case SpvCapabilitySubgroupBufferBlockIOINTEL: return "SubgroupBufferBlockIOINTEL"; + case SpvCapabilitySubgroupImageBlockIOINTEL: return "SubgroupImageBlockIOINTEL"; +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 655a79c..33b4a8b 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -1291,6 +1291,7 @@ enum Capability { + CapabilityCooperativeVectorTrainingNV = 5435, + CapabilityRayTracingClusterAccelerationStructureNV = 5437, + CapabilityTensorAddressingNV = 5439, ++ CapabilityCooperativeMatrixDecodeVectorNV = 5447, + CapabilitySubgroupShuffleINTEL = 5568, + CapabilitySubgroupBufferBlockIOINTEL = 5569, + CapabilitySubgroupImageBlockIOINTEL = 5570, +@@ -1579,6 +1580,7 @@ enum TensorClampMode { + enum TensorAddressingOperandsShift { + TensorAddressingOperandsTensorViewShift = 0, + TensorAddressingOperandsDecodeFuncShift = 1, ++ TensorAddressingOperandsDecodeVectorFuncShift = 2, + TensorAddressingOperandsMax = 0x7fffffff, + }; + +@@ -1586,6 +1588,7 @@ enum TensorAddressingOperandsMask { + TensorAddressingOperandsMaskNone = 0, + TensorAddressingOperandsTensorViewMask = 0x00000001, + TensorAddressingOperandsDecodeFuncMask = 0x00000002, ++ TensorAddressingOperandsDecodeVectorFuncMask = 0x00000004, + }; + + enum TensorOperandsShift { +@@ -4453,6 +4456,7 @@ inline const char* CapabilityToString(Capability value) { + case CapabilityCooperativeVectorTrainingNV: return "CooperativeVectorTrainingNV"; + case CapabilityRayTracingClusterAccelerationStructureNV: return "RayTracingClusterAccelerationStructureNV"; + case CapabilityTensorAddressingNV: return "TensorAddressingNV"; ++ case CapabilityCooperativeMatrixDecodeVectorNV: return "CooperativeMatrixDecodeVectorNV"; + case CapabilitySubgroupShuffleINTEL: return "SubgroupShuffleINTEL"; + case CapabilitySubgroupBufferBlockIOINTEL: return "SubgroupBufferBlockIOINTEL"; + case CapabilitySubgroupImageBlockIOINTEL: return "SubgroupImageBlockIOINTEL"; +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index 270b33f..eb15ea2 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -1291,6 +1291,7 @@ enum class Capability : unsigned { + CooperativeVectorTrainingNV = 5435, + RayTracingClusterAccelerationStructureNV = 5437, + TensorAddressingNV = 5439, ++ CooperativeMatrixDecodeVectorNV = 5447, + SubgroupShuffleINTEL = 5568, + SubgroupBufferBlockIOINTEL = 5569, + SubgroupImageBlockIOINTEL = 5570, +@@ -1579,6 +1580,7 @@ enum class TensorClampMode : unsigned { + enum class TensorAddressingOperandsShift : unsigned { + TensorView = 0, + DecodeFunc = 1, ++ DecodeVectorFunc = 2, + Max = 0x7fffffff, + }; + +@@ -1586,6 +1588,7 @@ enum class TensorAddressingOperandsMask : unsigned { + MaskNone = 0, + TensorView = 0x00000001, + DecodeFunc = 0x00000002, ++ DecodeVectorFunc = 0x00000004, + }; + + enum class TensorOperandsShift : unsigned { +@@ -4453,6 +4456,7 @@ inline const char* CapabilityToString(Capability value) { + case Capability::CooperativeVectorTrainingNV: return "CooperativeVectorTrainingNV"; + case Capability::RayTracingClusterAccelerationStructureNV: return "RayTracingClusterAccelerationStructureNV"; + case Capability::TensorAddressingNV: return "TensorAddressingNV"; ++ case Capability::CooperativeMatrixDecodeVectorNV: return "CooperativeMatrixDecodeVectorNV"; + case Capability::SubgroupShuffleINTEL: return "SubgroupShuffleINTEL"; + case Capability::SubgroupBufferBlockIOINTEL: return "SubgroupBufferBlockIOINTEL"; + case Capability::SubgroupImageBlockIOINTEL: return "SubgroupImageBlockIOINTEL"; +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 5a21f07..35f85d9 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -1257,6 +1257,7 @@ + "CooperativeVectorTrainingNV": 5435, + "RayTracingClusterAccelerationStructureNV": 5437, + "TensorAddressingNV": 5439, ++ "CooperativeMatrixDecodeVectorNV": 5447, + "SubgroupShuffleINTEL": 5568, + "SubgroupBufferBlockIOINTEL": 5569, + "SubgroupImageBlockIOINTEL": 5570, +@@ -1551,7 +1552,8 @@ + "Values": + { + "TensorView": 0, +- "DecodeFunc": 1 ++ "DecodeFunc": 1, ++ "DecodeVectorFunc": 2 + } + }, + { +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index 64b0a1f..f244e9a 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -1282,6 +1282,7 @@ spv = { + CooperativeVectorTrainingNV = 5435, + RayTracingClusterAccelerationStructureNV = 5437, + TensorAddressingNV = 5439, ++ CooperativeMatrixDecodeVectorNV = 5447, + SubgroupShuffleINTEL = 5568, + SubgroupBufferBlockIOINTEL = 5569, + SubgroupImageBlockIOINTEL = 5570, +@@ -1570,6 +1571,7 @@ spv = { + TensorAddressingOperandsShift = { + TensorView = 0, + DecodeFunc = 1, ++ DecodeVectorFunc = 2, + Max = 0x7fffffff, + }, + +@@ -1577,6 +1579,7 @@ spv = { + MaskNone = 0, + TensorView = 0x00000001, + DecodeFunc = 0x00000002, ++ DecodeVectorFunc = 0x00000004, + }, + + TensorOperandsShift = { +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index 5f3bae6..af0e61f 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -1253,6 +1253,7 @@ spv = { + 'CooperativeVectorTrainingNV' : 5435, + 'RayTracingClusterAccelerationStructureNV' : 5437, + 'TensorAddressingNV' : 5439, ++ 'CooperativeMatrixDecodeVectorNV' : 5447, + 'SubgroupShuffleINTEL' : 5568, + 'SubgroupBufferBlockIOINTEL' : 5569, + 'SubgroupImageBlockIOINTEL' : 5570, +@@ -1525,12 +1526,14 @@ spv = { + 'TensorAddressingOperandsShift' : { + 'TensorView' : 0, + 'DecodeFunc' : 1, ++ 'DecodeVectorFunc' : 2, + }, + + 'TensorAddressingOperandsMask' : { + 'MaskNone' : 0, + 'TensorView' : 0x00000001, + 'DecodeFunc' : 0x00000002, ++ 'DecodeVectorFunc' : 0x00000004, + }, + + 'TensorOperandsShift' : { +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 4e4e3dc..1ed7d76 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -1327,6 +1327,7 @@ enum Capability : uint + CooperativeVectorTrainingNV = 5435, + RayTracingClusterAccelerationStructureNV = 5437, + TensorAddressingNV = 5439, ++ CooperativeMatrixDecodeVectorNV = 5447, + SubgroupShuffleINTEL = 5568, + SubgroupBufferBlockIOINTEL = 5569, + SubgroupImageBlockIOINTEL = 5570, +@@ -1635,6 +1636,7 @@ enum TensorAddressingOperandsShift : uint + { + TensorView = 0, + DecodeFunc = 1, ++ DecodeVectorFunc = 2, + Max = 0x7fffffff, + } + +@@ -1643,6 +1645,7 @@ enum TensorAddressingOperandsMask : uint + MaskNone = 0, + TensorView = 0x00000001, + DecodeFunc = 0x00000002, ++ DecodeVectorFunc = 0x00000004, + } + + enum TensorOperandsShift : uint +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0016-Add-ArmExperimentalMLOperations-instruction-set-602.patch b/internal/rosa/package/spirv/0016-Add-ArmExperimentalMLOperations-instruction-set-602.patch new file mode 100644 index 00000000..eb829a3d --- /dev/null +++ b/internal/rosa/package/spirv/0016-Add-ArmExperimentalMLOperations-instruction-set-602.patch @@ -0,0 +1,116 @@ +From 8c5559c134abcf432ec59db842404087b9906c1a Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?K=C3=A9vin=20Petit?= <kevin.petit@arm.com> +Date: Wed, 20 May 2026 16:39:51 +0100 +Subject: [PATCH 16/26] Add ArmExperimentalMLOperations instruction set (#602) + +Change-Id: Id5e6f036ed0a1653ea9817c1d5b193c58403fe1d + +Signed-off-by: Kevin Petit <kevin.petit@arm.com> +--- + BUILD.bazel | 6 +++++ + .../unified1/ArmExperimentalMLOperations.h | 26 +++++++++++++++++++ + ...rm.experimental-ml-operations.grammar.json | 25 ++++++++++++++++++ + tools/buildHeaders/bin/makeExtinstHeaders.py | 1 + + 4 files changed, 58 insertions(+) + create mode 100644 include/spirv/unified1/ArmExperimentalMLOperations.h + create mode 100644 include/spirv/unified1/extinst.arm.experimental-ml-operations.grammar.json + +diff --git a/BUILD.bazel b/BUILD.bazel +index 61ef7e8..db21aeb 100644 +--- a/BUILD.bazel ++++ b/BUILD.bazel +@@ -143,6 +143,11 @@ filegroup( + srcs = ["include/spirv/unified1/extinst.nonsemantic.graph.debuginfo.grammar.json"], + ) + ++filegroup( ++ name = "spirv_ext_inst_arm_experimental_ml_operations", ++ srcs = ["include/spirv/unified1/extinst.arm.experimental-ml-operations.grammar.json"], ++) ++ + cc_library( + name = "spirv_common_headers", + hdrs = [ +@@ -152,6 +157,7 @@ cc_library( + "include/spirv/1.1/OpenCL.std.h", + "include/spirv/1.2/GLSL.std.450.h", + "include/spirv/1.2/OpenCL.std.h", ++ "include/spirv/unified1/ArmExperimentalMLOperations.h", + "include/spirv/unified1/ArmMotionEngine.100.h", + "include/spirv/unified1/GLSL.std.450.h", + "include/spirv/unified1/NonSemanticClspvReflection.h", +diff --git a/include/spirv/unified1/ArmExperimentalMLOperations.h b/include/spirv/unified1/ArmExperimentalMLOperations.h +new file mode 100644 +index 0000000..64b0e70 +--- /dev/null ++++ b/include/spirv/unified1/ArmExperimentalMLOperations.h +@@ -0,0 +1,26 @@ ++// SPDX-FileCopyrightText: 2025 Arm Ltd. ++// SPDX-License-Identifier: MIT ++ ++#ifndef SPIRV_UNIFIED1_ArmExperimentalMLOperations_H_ ++#define SPIRV_UNIFIED1_ArmExperimentalMLOperations_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++enum { ++ ArmExperimentalMLOperationsRevision = 1, ++ ArmExperimentalMLOperationsRevision_BitWidthPadding = 0x7fffffff ++}; ++ ++enum ArmExperimentalMLOperationsInstructions { ++ ArmExperimentalMLOperationsCALL = 0, ++ ArmExperimentalMLOperationsInstructionsMax = 0x7fffffff ++}; ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // SPIRV_UNIFIED1_ArmExperimentalMLOperations_H_ +diff --git a/include/spirv/unified1/extinst.arm.experimental-ml-operations.grammar.json b/include/spirv/unified1/extinst.arm.experimental-ml-operations.grammar.json +new file mode 100644 +index 0000000..169dfe9 +--- /dev/null ++++ b/include/spirv/unified1/extinst.arm.experimental-ml-operations.grammar.json +@@ -0,0 +1,25 @@ ++{ ++ "copyright": [ ++ "SPDX-FileCopyrightText: 2025 Arm Ltd.", ++ "SPDX-License-Identifier: MIT" ++ ], ++ "revision": 1, ++ "instructions": [ ++ { ++ "opname": "CALL", ++ "opcode": 0, ++ "operands": [ ++ { ++ "kind": "LiteralInteger", ++ "name": "Opcode" ++ }, ++ { ++ "kind": "IdRef", ++ "quantifier": "*", ++ "name": "Parameters" ++ } ++ ] ++ } ++ ], ++ "operand_kinds": [] ++} +diff --git a/tools/buildHeaders/bin/makeExtinstHeaders.py b/tools/buildHeaders/bin/makeExtinstHeaders.py +index 1c9fbfd..863fca1 100755 +--- a/tools/buildHeaders/bin/makeExtinstHeaders.py ++++ b/tools/buildHeaders/bin/makeExtinstHeaders.py +@@ -32,3 +32,4 @@ mk_extinst('NonSemanticVkspReflection', 'extinst.nonsemantic.vkspreflection.gram + mk_extinst('TOSA', 'extinst.tosa.001000.1.grammar.json', 'TOSA.001000.1') + mk_extinst('ArmMotionEngine', 'extinst.arm.motion-engine.100.grammar.json', 'ArmMotionEngine.100') + mk_extinst('NonSemanticGraphDebugInfo', 'extinst.nonsemantic.graph.debuginfo.grammar.json') ++mk_extinst('ArmExperimentalMLOperations', 'extinst.arm.experimental-ml-operations.grammar.json') +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0017-Add-Pred-as-a-new-SPIR-V-source-language-606.patch b/internal/rosa/package/spirv/0017-Add-Pred-as-a-new-SPIR-V-source-language-606.patch new file mode 100644 index 00000000..b684f049 --- /dev/null +++ b/internal/rosa/package/spirv/0017-Add-Pred-as-a-new-SPIR-V-source-language-606.patch @@ -0,0 +1,207 @@ +From 1e770e7de8373a8dd49f23416cf7ca4001d01040 Mon Sep 17 00:00:00 2001 +From: Jebrim <jebscapeplugin@gmail.com> +Date: Wed, 27 May 2026 10:48:38 -0500 +Subject: [PATCH 17/26] Add Pred as a new SPIR-V source language (#606) + +* Add Pred as a new SPIR-V source language + +* Update spirv.bf + +* Update spirv.core.grammar.json + +* Update spirv.cs + +* Update spirv.hpp + +* Update spirv.hpp11 + +* Update spirv.json + +* Update spirv.lua + +* Update spirv.py + +* Update spv.d + +* Update spir-v.xml +--- + include/spirv/spir-v.xml | 3 ++- + include/spirv/unified1/spirv.bf | 1 + + include/spirv/unified1/spirv.core.grammar.json | 5 +++++ + include/spirv/unified1/spirv.cs | 1 + + include/spirv/unified1/spirv.h | 2 ++ + include/spirv/unified1/spirv.hpp | 2 ++ + include/spirv/unified1/spirv.hpp11 | 2 ++ + include/spirv/unified1/spirv.json | 3 ++- + include/spirv/unified1/spirv.lua | 1 + + include/spirv/unified1/spirv.py | 1 + + include/spirv/unified1/spv.d | 1 + + 11 files changed, 20 insertions(+), 2 deletions(-) + +diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml +index 69a2c2a..1463dd6 100644 +--- a/include/spirv/spir-v.xml ++++ b/include/spirv/spir-v.xml +@@ -82,7 +82,8 @@ + <id value="47" vendor="ARM" comment="Contact Christopher Gautier, christopher.gautier@arm.com"/> + <id value="48" vendor="Goopax" comment="Contact Ingo Josopait, josopait@goopax.com"/> + <id value="49" vendor="Icyllis Milica" tool="Arc3D Shader Compiler" comment="Contact Icyllis Milica, https://github.com/BloCamLimb/Arc3D"/> +- <unused start="50" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/> ++ <id value="50" vendor="Isochron" tool="Pred" comment="Contact Justin Ead, jebrim@isochrontechnologies.com"/> ++ <unused start="51" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/> + </ids> + + <!-- SECTION: SPIR-V Opcodes and Enumerants --> +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index 9497023..fb9644e 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -56,6 +56,7 @@ namespace Spv + Slang = 11, + Zig = 12, + Rust = 13, ++ Pred = 14, + Max = 0x7fffffff, + } + +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 4f96982..9e1adee 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -12684,6 +12684,11 @@ + "enumerant" : "Rust", + "value" : 13, + "version" : "1.0" ++ }, ++ { ++ "enumerant" : "Pred", ++ "value" : 14, ++ "version" : "1.0" + } + ] + }, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index 7631bf2..d0f69b9 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -55,6 +55,7 @@ namespace Spv + Slang = 11, + Zig = 12, + Rust = 13, ++ Pred = 14, + Max = 0x7fffffff, + } + +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 5ab265f..966ad68 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -63,6 +63,7 @@ typedef enum SpvSourceLanguage_ { + SpvSourceLanguageSlang = 11, + SpvSourceLanguageZig = 12, + SpvSourceLanguageRust = 13, ++ SpvSourceLanguagePred = 14, + SpvSourceLanguageMax = 0x7fffffff, + } SpvSourceLanguage; + +@@ -3564,6 +3565,7 @@ inline const char* SpvSourceLanguageToString(SpvSourceLanguage value) { + case SpvSourceLanguageSlang: return "Slang"; + case SpvSourceLanguageZig: return "Zig"; + case SpvSourceLanguageRust: return "Rust"; ++ case SpvSourceLanguagePred: return "Pred"; + default: return "Unknown"; + } + } +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 33b4a8b..517b7cf 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -59,6 +59,7 @@ enum SourceLanguage { + SourceLanguageSlang = 11, + SourceLanguageZig = 12, + SourceLanguageRust = 13, ++ SourceLanguagePred = 14, + SourceLanguageMax = 0x7fffffff, + }; + +@@ -3560,6 +3561,7 @@ inline const char* SourceLanguageToString(SourceLanguage value) { + case SourceLanguageSlang: return "Slang"; + case SourceLanguageZig: return "Zig"; + case SourceLanguageRust: return "Rust"; ++ case SourceLanguagePred: return "Pred"; + default: return "Unknown"; + } + } +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index eb15ea2..4fa5f8f 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -59,6 +59,7 @@ enum class SourceLanguage : unsigned { + Slang = 11, + Zig = 12, + Rust = 13, ++ Pred = 14, + Max = 0x7fffffff, + }; + +@@ -3560,6 +3561,7 @@ inline const char* SourceLanguageToString(SourceLanguage value) { + case SourceLanguage::Slang: return "Slang"; + case SourceLanguage::Zig: return "Zig"; + case SourceLanguage::Rust: return "Rust"; ++ case SourceLanguage::Pred: return "Pred"; + default: return "Unknown"; + } + } +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 35f85d9..43a7891 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -65,7 +65,8 @@ + "WGSL": 10, + "Slang": 11, + "Zig": 12, +- "Rust": 13 ++ "Rust": 13, ++ "Pred": 14 + } + }, + { +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index f244e9a..bb4c52f 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -50,6 +50,7 @@ spv = { + Slang = 11, + Zig = 12, + Rust = 13, ++ Pred = 14, + Max = 0x7fffffff, + }, + +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index af0e61f..e01e462 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -50,6 +50,7 @@ spv = { + 'Slang' : 11, + 'Zig' : 12, + 'Rust' : 13, ++ 'Pred' : 14, + }, + + 'ExecutionModel' : { +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 1ed7d76..3e631ef 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -58,6 +58,7 @@ enum SourceLanguage : uint + Slang = 11, + Zig = 12, + Rust = 13, ++ Pred = 14, + Max = 0x7fffffff, + } + +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0018-added-source-language-entry-ApilaJai-607.patch b/internal/rosa/package/spirv/0018-added-source-language-entry-ApilaJai-607.patch new file mode 100644 index 00000000..021aa95c --- /dev/null +++ b/internal/rosa/package/spirv/0018-added-source-language-entry-ApilaJai-607.patch @@ -0,0 +1,186 @@ +From c63848ecf2200425511319fd8bf2c17b751e501e Mon Sep 17 00:00:00 2001 +From: apilatosba <104633944+apilatosba@users.noreply.github.com> +Date: Wed, 17 Jun 2026 17:38:53 +0200 +Subject: [PATCH 18/26] added source language entry ApilaJai (#607) + +--- + include/spirv/spir-v.xml | 3 ++- + include/spirv/unified1/spirv.bf | 1 + + include/spirv/unified1/spirv.core.grammar.json | 5 +++++ + include/spirv/unified1/spirv.cs | 1 + + include/spirv/unified1/spirv.h | 2 ++ + include/spirv/unified1/spirv.hpp | 2 ++ + include/spirv/unified1/spirv.hpp11 | 2 ++ + include/spirv/unified1/spirv.json | 3 ++- + include/spirv/unified1/spirv.lua | 1 + + include/spirv/unified1/spirv.py | 1 + + include/spirv/unified1/spv.d | 1 + + 11 files changed, 20 insertions(+), 2 deletions(-) + +diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml +index 1463dd6..1b083a4 100644 +--- a/include/spirv/spir-v.xml ++++ b/include/spirv/spir-v.xml +@@ -83,7 +83,8 @@ + <id value="48" vendor="Goopax" comment="Contact Ingo Josopait, josopait@goopax.com"/> + <id value="49" vendor="Icyllis Milica" tool="Arc3D Shader Compiler" comment="Contact Icyllis Milica, https://github.com/BloCamLimb/Arc3D"/> + <id value="50" vendor="Isochron" tool="Pred" comment="Contact Justin Ead, jebrim@isochrontechnologies.com"/> +- <unused start="51" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/> ++ <id value="51" vendor="apilatosba" tool="Apila Jai Compiler" comment="https://github.com/apilatosba/jai_to_spirv_compiler"/> ++ <unused start="52" end="0xFFFF" comment="Tool ID range reservable for future use by vendors"/> + </ids> + + <!-- SECTION: SPIR-V Opcodes and Enumerants --> +diff --git a/include/spirv/unified1/spirv.bf b/include/spirv/unified1/spirv.bf +index fb9644e..40fbfff 100644 +--- a/include/spirv/unified1/spirv.bf ++++ b/include/spirv/unified1/spirv.bf +@@ -57,6 +57,7 @@ namespace Spv + Zig = 12, + Rust = 13, + Pred = 14, ++ ApilaJai = 15, + Max = 0x7fffffff, + } + +diff --git a/include/spirv/unified1/spirv.core.grammar.json b/include/spirv/unified1/spirv.core.grammar.json +index 9e1adee..8b5595c 100644 +--- a/include/spirv/unified1/spirv.core.grammar.json ++++ b/include/spirv/unified1/spirv.core.grammar.json +@@ -12689,6 +12689,11 @@ + "enumerant" : "Pred", + "value" : 14, + "version" : "1.0" ++ }, ++ { ++ "enumerant" : "ApilaJai", ++ "value" : 15, ++ "version" : "1.0" + } + ] + }, +diff --git a/include/spirv/unified1/spirv.cs b/include/spirv/unified1/spirv.cs +index d0f69b9..a1b7d58 100644 +--- a/include/spirv/unified1/spirv.cs ++++ b/include/spirv/unified1/spirv.cs +@@ -56,6 +56,7 @@ namespace Spv + Zig = 12, + Rust = 13, + Pred = 14, ++ ApilaJai = 15, + Max = 0x7fffffff, + } + +diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h +index 966ad68..d1f88cf 100644 +--- a/include/spirv/unified1/spirv.h ++++ b/include/spirv/unified1/spirv.h +@@ -64,6 +64,7 @@ typedef enum SpvSourceLanguage_ { + SpvSourceLanguageZig = 12, + SpvSourceLanguageRust = 13, + SpvSourceLanguagePred = 14, ++ SpvSourceLanguageApilaJai = 15, + SpvSourceLanguageMax = 0x7fffffff, + } SpvSourceLanguage; + +@@ -3566,6 +3567,7 @@ inline const char* SpvSourceLanguageToString(SpvSourceLanguage value) { + case SpvSourceLanguageZig: return "Zig"; + case SpvSourceLanguageRust: return "Rust"; + case SpvSourceLanguagePred: return "Pred"; ++ case SpvSourceLanguageApilaJai: return "ApilaJai"; + default: return "Unknown"; + } + } +diff --git a/include/spirv/unified1/spirv.hpp b/include/spirv/unified1/spirv.hpp +index 517b7cf..9f3cb01 100644 +--- a/include/spirv/unified1/spirv.hpp ++++ b/include/spirv/unified1/spirv.hpp +@@ -60,6 +60,7 @@ enum SourceLanguage { + SourceLanguageZig = 12, + SourceLanguageRust = 13, + SourceLanguagePred = 14, ++ SourceLanguageApilaJai = 15, + SourceLanguageMax = 0x7fffffff, + }; + +@@ -3562,6 +3563,7 @@ inline const char* SourceLanguageToString(SourceLanguage value) { + case SourceLanguageZig: return "Zig"; + case SourceLanguageRust: return "Rust"; + case SourceLanguagePred: return "Pred"; ++ case SourceLanguageApilaJai: return "ApilaJai"; + default: return "Unknown"; + } + } +diff --git a/include/spirv/unified1/spirv.hpp11 b/include/spirv/unified1/spirv.hpp11 +index 4fa5f8f..4eb6fbd 100644 +--- a/include/spirv/unified1/spirv.hpp11 ++++ b/include/spirv/unified1/spirv.hpp11 +@@ -60,6 +60,7 @@ enum class SourceLanguage : unsigned { + Zig = 12, + Rust = 13, + Pred = 14, ++ ApilaJai = 15, + Max = 0x7fffffff, + }; + +@@ -3562,6 +3563,7 @@ inline const char* SourceLanguageToString(SourceLanguage value) { + case SourceLanguage::Zig: return "Zig"; + case SourceLanguage::Rust: return "Rust"; + case SourceLanguage::Pred: return "Pred"; ++ case SourceLanguage::ApilaJai: return "ApilaJai"; + default: return "Unknown"; + } + } +diff --git a/include/spirv/unified1/spirv.json b/include/spirv/unified1/spirv.json +index 43a7891..1b124e4 100644 +--- a/include/spirv/unified1/spirv.json ++++ b/include/spirv/unified1/spirv.json +@@ -66,7 +66,8 @@ + "Slang": 11, + "Zig": 12, + "Rust": 13, +- "Pred": 14 ++ "Pred": 14, ++ "ApilaJai": 15 + } + }, + { +diff --git a/include/spirv/unified1/spirv.lua b/include/spirv/unified1/spirv.lua +index bb4c52f..a5f9267 100644 +--- a/include/spirv/unified1/spirv.lua ++++ b/include/spirv/unified1/spirv.lua +@@ -51,6 +51,7 @@ spv = { + Zig = 12, + Rust = 13, + Pred = 14, ++ ApilaJai = 15, + Max = 0x7fffffff, + }, + +diff --git a/include/spirv/unified1/spirv.py b/include/spirv/unified1/spirv.py +index e01e462..17cb6b1 100644 +--- a/include/spirv/unified1/spirv.py ++++ b/include/spirv/unified1/spirv.py +@@ -51,6 +51,7 @@ spv = { + 'Zig' : 12, + 'Rust' : 13, + 'Pred' : 14, ++ 'ApilaJai' : 15, + }, + + 'ExecutionModel' : { +diff --git a/include/spirv/unified1/spv.d b/include/spirv/unified1/spv.d +index 3e631ef..ceb9aac 100644 +--- a/include/spirv/unified1/spv.d ++++ b/include/spirv/unified1/spv.d +@@ -59,6 +59,7 @@ enum SourceLanguage : uint + Zig = 12, + Rust = 13, + Pred = 14, ++ ApilaJai = 15, + Max = 0x7fffffff, + } + +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0019-license-Add-or-update-REUSE-compliance-609.patch b/internal/rosa/package/spirv/0019-license-Add-or-update-REUSE-compliance-609.patch new file mode 100644 index 00000000..0b65793e --- /dev/null +++ b/internal/rosa/package/spirv/0019-license-Add-or-update-REUSE-compliance-609.patch @@ -0,0 +1,116 @@ +From ed734383000313dd53e57aec28b35effc28f8f61 Mon Sep 17 00:00:00 2001 +From: Khronos Group Web Services <webservices@khronosgroup.org> +Date: Wed, 24 Jun 2026 11:37:39 -0400 +Subject: [PATCH 19/26] license: Add or update REUSE compliance (#609) + +--- + CODE_OF_CONDUCT.md | 7 ++++++- + README.md | 5 +++++ + REUSE.toml | 42 ++++++++++++------------------------------ + SECURITY.md | 5 +++++ + 4 files changed, 28 insertions(+), 31 deletions(-) + +diff --git a/CODE_OF_CONDUCT.md b/CODE_OF_CONDUCT.md +index a11610b..f601007 100644 +--- a/CODE_OF_CONDUCT.md ++++ b/CODE_OF_CONDUCT.md +@@ -1 +1,6 @@ +-A reminder that this issue tracker is managed by the Khronos Group. Interactions here should follow the Khronos Code of Conduct (https://www.khronos.org/developers/code-of-conduct), which prohibits aggressive or derogatory language. Please keep the discussion friendly and civil. ++<!-- ++SPDX-FileCopyrightText: 2026 The Khronos Group Inc. ++SPDX-License-Identifier: CC-BY-4.0 ++--> ++ ++A reminder that this repository is managed by the Khronos Group. Interactions here should follow the Khronos Code of Conduct (https://www.khronos.org/developers/code-of-conduct), which prohibits aggressive or derogatory language. Please keep the discussion friendly and civil. +diff --git a/README.md b/README.md +index ed38828..16fa0cd 100644 +--- a/README.md ++++ b/README.md +@@ -1,3 +1,8 @@ ++<!-- ++SPDX-FileCopyrightText: 2026 The Khronos Group Inc. ++SPDX-License-Identifier: CC-BY-4.0 ++--> ++ + # SPIR-V Headers + + This repository contains machine-readable files for the +diff --git a/REUSE.toml b/REUSE.toml +index 8392272..00837a5 100644 +--- a/REUSE.toml ++++ b/REUSE.toml +@@ -4,46 +4,28 @@ SPDX-PackageSupplier = "The Khronos Group, Inc." + SPDX-PackageDownloadLocation = "https://github.com/KhronosGroup/SPIRV-Headers" + + [[annotations]] +-path = ["**.md", "WORKSPACE", ".git**"] +-precedence = "aggregate" ++path = [ ++ "WORKSPACE", ++ ".git**", ++] ++precedence = "closest" + SPDX-FileCopyrightText = "The Khronos Group, Inc." + SPDX-License-Identifier = "CC-BY-4.0" + + [[annotations]] +-path = ["include/**/*.json" ] +-precedence = "aggregate" ++path = ["**" ] ++precedence = "closest" + SPDX-FileCopyrightText = "The Khronos Group, Inc." + SPDX-License-Identifier = "MIT" + + [[annotations]] +-path = ["include/spirv/1.0/spir*", "include/spirv/1.1/spir*", "include/spirv/1.2/spir*"] +-precedence = "aggregate" +-SPDX-FileCopyrightText = "2014-2018 The Khronos Group, Inc." +-SPDX-License-Identifier = "MIT" +- +-[[annotations]] +-path = ["include/spirv/unified1/spir*", "include/spirv/unified1/spv.d"] +-precedence = "aggregate" +-SPDX-FileCopyrightText = "2014-2024 The Khronos Group, Inc." +-SPDX-License-Identifier = "MIT" +- +-[[annotations]] +-path = [ +- "BUILD.bazel", +- "MODULE.bazel", +- "cmake/SPIRV-Headers.pc.in", +- "tools/buildHeaders/CMakeLists.txt", +- "tools/buildHeaders/bin/makeExtinstHeaders.py", +- "tools/buildHeaders/bin/makeHeaders", +- "include/spirv/unified1/OpenCLDebugInfo100.h", +- "include/spirv/unified1/DebugInfo.h" +-] +-precedence = "aggregate" +-SPDX-FileCopyrightText = "The Khronos Group, Inc." ++path = "tools/buildHeaders/bin/generate_language_headers.py" ++precedence = "closest" ++SPDX-FileCopyrightText = "Google LLC" + SPDX-License-Identifier = "MIT" + + [[annotations]] + path = "tools/buildHeaders/jsoncpp/**" +-precedence = "aggregate" +-SPDX-FileCopyrightText = "2007-2010 by Baptiste Lepilleur" ++precedence = "closest" ++SPDX-FileCopyrightText = "Baptiste Lepilleur" + SPDX-License-Identifier = "MIT" +diff --git a/SECURITY.md b/SECURITY.md +index 9b51f0c..cdc2060 100644 +--- a/SECURITY.md ++++ b/SECURITY.md +@@ -1,3 +1,8 @@ ++<!-- ++SPDX-FileCopyrightText: 2026 The Khronos Group Inc. ++SPDX-License-Identifier: CC-BY-4.0 ++--> ++ + # Security Policy + + ## Supported Versions +-- +2.54.0 + diff --git a/internal/rosa/package/spirv/0020-chore-Add-CONTRIBUTING-file-608.patch b/internal/rosa/package/spirv/0020-chore-Add-CONTRIBUTING-file-608.patch new file mode 100644 index 00000000..e97bb809 --- /dev/null +++ b/internal/rosa/package/spirv/0020-chore-Add-CONTRIBUTING-file-608.patch @@ -0,0 +1,47 @@ +From daa093dd29aab8cbb6562b808370562f56e399fb Mon Sep 17 00:00:00 2001 +From: Khronos Group Web Services <webservices@khronosgroup.org> +Date: Wed, 24 Jun 2026 11:39:24 -0400 +Subject: [PATCH 20/26] chore: Add CONTRIBUTING file (#608) + +--- + CONTRIBUTING.md | 28 ++++++++++++++++++++++++++++ + 1 file changed, 28 insertions(+) + create mode 100644 CONTRIBUTING.md + +diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md +new file mode 100644 +index 0000000..3d3062c +--- /dev/null ++++ b/CONTRIBUTING.md +@@ -0,0 +1,28 @@ ++<!-- ++SPDX-FileCopyrightText: 2026 The Khronos Group Inc. ++SPDX-License-Identifier: CC-BY-4.0 ++--> ++ ++# Contributing to SPIRV-Headers ++ ++## Contributing ++ ++This project welcomes contributions and suggestions. Contributions require you ++to agree to a ++[Contributor License Agreement (CLA)](https://cla-assistant.io/KhronosGroup/SPIRV-Headers) ++declaring that you have the right to, and actually do, grant the rights to use ++your contribution. ++ ++When you submit a pull request, a CLA bot will determine whether you need to ++sign a CLA. Simply follow the instructions provided. ++ ++## AI-Assisted Contributions ++ ++By submitting a Contribution to this repository, you additionally represent ++that, to the extent any of Your Contributions were developed with the ++assistance of artificial intelligence tools or AI-generated code, You have ++exercised sufficient review, judgment, and creative direction over such tools ++and resulting material to reasonably consider it Your original creation, and ++You are not aware of any third-party license, intellectual property claim, or ++other restriction arising from such use that is associated with any part of ++Your Contribution or use thereof. +-- +2.54.0 + diff --git a/internal/rosa/package/spirv.az b/internal/rosa/package/spirv/package.az index 2fcbc7be..37b07162 100644 --- a/internal/rosa/package/spirv.az +++ b/internal/rosa/package/spirv/package.az @@ -12,6 +12,29 @@ package spirv-headers { checksum = "6cmvMCH5aiHykXcozckfMOVA0nm0am4Xr2g9swBB9FtOV1vYBHgats5aRv4uQ9Kq"; }; + patches = [ + "0001-grammar-and-header-changes-for-SPV_INTEL_predicated_.patch", + "0002-header-updates-for-SPV_INTEL_rounded_divide_sqrt-582.patch", + "0003-Add-SPV_MESA_fragment_coverage_mask-enumerants-580.patch", + "0004-Update-headers-for-spirv-issue-373-584.patch", + "0005-Reserve-some-tokens-for-Samsung-586.patch", + "0006-Fix-OpCompositeConstructContinuedINTEL-operands-587.patch", + "0007-Update-spirv.core.grammar.json-revision-593.patch", + "0008-Reserve-ImageOperand-17-for-Google-589.patch", + "0009-Fix-OpReadPipeBlockingINTEL-OpWritePipeBlockingINTEL.patch", + "0010-Add-SPV_AMD_weak_linkage-extension-583.patch", + "0011-Add-SPV_KHR_opacity_micromap-599.patch", + "0012-Add-NonSemanticGraphDebugInfo-instruction-set-591.patch", + "0013-Revert-Add-SPV_MESA_fragment_coverage_mask-enumerant.patch", + "0014-SPV_EXT_split_barrier-600.patch", + "0015-SPV_NV_cooperative_matrix_decode_vector-601.patch", + "0016-Add-ArmExperimentalMLOperations-instruction-set-602.patch", + "0017-Add-Pred-as-a-new-SPIR-V-source-language-606.patch", + "0018-added-source-language-entry-ApilaJai-607.patch", + "0019-license-Add-or-update-REUSE-compliance-609.patch", + "0020-chore-Add-CONTRIBUTING-file-608.patch", + ]; + exec = cmake { // upstream has no tests skipTest = true; @@ -24,11 +47,11 @@ package spirv-tools { anitya = 14894; latest = anityaFallback; - version# = "2026.1"; + version# = "2026.2"; source = remoteGitHub { suffix = "KhronosGroup/SPIRV-Tools"; tag = "v"+version; - checksum = "ZSQPQx8NltCDzQLk4qlaVxyWRWeI_JtsjEpeFt3kezTanl9DTHfLixSUCezMFBjv"; + checksum = "pJ78inb4VzLy8CjQOESpIHHGYVVOR6qN-ZqB-2MzGTcKaoYb3bqhSjkKupiaJzIk"; }; exec = cmake { |